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Thu, 29 Jan 2026 07:59:29 -0800 (PST) Received: from draig.lan ([185.124.0.126]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e131cf16sm16376335f8f.22.2026.01.29.07.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 07:59:28 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 06FF85F878; Thu, 29 Jan 2026 15:59:28 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Manos Pitsidianakis Subject: Re: [PATCH v2 6/6] target/arm: Permit configurations with SME but not SVE In-Reply-To: <20260129113455.1283266-7-peter.maydell@linaro.org> (Peter Maydell's message of "Thu, 29 Jan 2026 11:34:55 +0000") References: <20260129113455.1283266-1-peter.maydell@linaro.org> <20260129113455.1283266-7-peter.maydell@linaro.org> User-Agent: mu4e 1.14.0-pre1; emacs 30.1 Date: Thu, 29 Jan 2026 15:59:27 +0000 Message-ID: <877bt08l5s.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Peter Maydell writes: > In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled") > we added code that forces SME to be disabled if SVE is disabled. > This was something we did in the run-up to a release to avoid an > assertion failure in smcr_write() if the user disabled SVE on the > 'max' CPU without disabling SME also. > > Now that we have corrected the code so that it doesn't assert > in an SME-without-SVE setup, we can let users select it. > > This effectively reverts f7767ca30179. > > Note that this now means that command lines like "-cpu max,sve=3Doff" > which used to turn off SME and SVE will now give you a CPU with SME > but not SVE. This is permitted by our loose "max can always give you > extra stuff" rules, but may be unexpected to users. Mention this in > the CPU property documentation. > > Reviewed-by: Richard Henderson > Signed-off-by: Peter Maydell > --- > docs/system/arm/cpu-features.rst | 10 ++++++++-- > target/arm/cpu.c | 10 ---------- > 2 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-featu= res.rst > index 37d5dfd15b..9d0c5731cc 100644 > --- a/docs/system/arm/cpu-features.rst > +++ b/docs/system/arm/cpu-features.rst > @@ -318,12 +318,18 @@ SVE CPU Property Parsing Semantics > provided an error will be generated. To avoid this error, one must > enable at least one vector length prior to enabling SVE. >=20=20 > + 10) Disabling SVE does not automatically disable SME. If you want to > + disable both you must use ``sve=3Doff,sme=3Doff``. In particular, > + for the ``max`` CPU, ``sve=3Doff`` alone will give you a CPU with > + SME only (and which therefore still has the SVE vector registers). > + Most users will want to disable both at once. > + > SVE CPU Property Examples > ------------------------- >=20=20 > - 1) Disable SVE:: > + 1) Disable SVE and SME:: >=20=20 > - $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff > + $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff,sme=3Doff >=20=20 > 2) Implicitly enable all vector lengths for the ``max`` CPU type:: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro