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Wed, 27 Aug 2025 23:03:38 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 120e70de-839a-11f0-aeb2-fb57b961d000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=peduJ9WTSu7E+j7iCSxL49JBlP08f1gjaH5MGl5wIPualGeA6iid8c7tW3oNPa5C99f/QSS5fDoEDdtiZRciZmqTaRowQtaR70mHXXUokcTLhDuWn55/XYQcb55DfgyIr3jwlMvwKbph7Tv0UJCx93ycVivuJzqQUdlsvBGpgJYnFwc0tQVNZqBNJXTcLNid4DX8kH0E6KZG/sqZs+KdFmv9+c4Lzn2VvkGMEZl52rlHwvqHgc2kR3codCL70T5R9mlcmK8yIao8ylo6tjyk6ivXSxMppdtcx2yR2VG/qwQqgZwFvmnnfBcgOQx694mkoWrJe0LvJkSBrSJCzpsNtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22435f30-d8fb-4a26-37d4-08dde5bdf518 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Aug 2025 23:03:37.9933 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ovdffDZdCFrMEV8Ow9IZ7IUmQhZIBoluhcdJxDxU59dbvOvt79tI9GpKc+mxTMOjS7Qz+fO956xLhhJz3GFOKp0ZrAEsWNGOZHoi2XAo634= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6324 Hi Loenid, Leonid Komarianskyi writes: > The Dom0 and DomUs logic for the dom0less configuration in create_dom0() = and > arch_create_domUs() has been updated to account for extended SPIs when > supported by the hardware and enabled with CONFIG_GICV3_ESPI. These chang= es > ensure the proper calculation of the maximum number of SPIs and eSPIs ava= ilable > to Dom0 and DomUs in dom0less setups. > > When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled= , the > maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID > offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure > compatibility with non-Dom0 domains, this adjustment is applied by the > toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is > handled directly during VGIC initialization. If eSPIs are not supported, = the > calculation defaults to using the standard SPI range, with a maximum valu= e of > 992 interrupt lines, as it works currently. > > Signed-off-by: Leonid Komarianskyi Reviewed-by: Volodymyr Babchuk > > --- > Changes in V4: > - consolidated the eSPI and SPI logic into a new inline function, > vgic_def_nr_spis. Without eSPI support (either due to config being > disabled or hardware not supporting it), it will return the regular SPI > range, as it works currently. There are no functional changes compared > with the previous patch version > - removed VGIC_DEF_MAX_SPI macro, to reduce the number of ifdefs > > Changes in V3: > - renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI > - added eSPI initialization for dom0less setups > - fixed comment with mentions about dom0less builds > - fixed formatting for lines with more than 80 symbols > - updated commit message > > Changes in V2: > - no changes > --- > xen/arch/arm/dom0less-build.c | 2 +- > xen/arch/arm/domain_build.c | 2 +- > xen/arch/arm/include/asm/vgic.h | 21 +++++++++++++++++++++ > 3 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.= c > index 69b9ea22ce..02d5559102 100644 > --- a/xen/arch/arm/dom0less-build.c > +++ b/xen/arch/arm/dom0less-build.c > @@ -285,7 +285,7 @@ void __init arch_create_domUs(struct dt_device_node *= node, > { > int vpl011_virq =3D GUEST_VPL011_SPI; > =20 > - d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS; > + d_cfg->arch.nr_spis =3D vgic_def_nr_spis(); > =20 > /* > * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index d91a71acfd..39eea0be00 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -2054,7 +2054,7 @@ void __init create_dom0(void) > =20 > /* The vGIC for DOM0 is exactly emulating the hardware GIC */ > dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE; > - dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS; > + dom0_cfg.arch.nr_spis =3D vgic_def_nr_spis(); > dom0_cfg.arch.tee_type =3D tee_get_type(); > dom0_cfg.max_vcpus =3D dom0_max_vcpus(); > =20 > diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v= gic.h > index fb4cea73eb..11f9d216eb 100644 > --- a/xen/arch/arm/include/asm/vgic.h > +++ b/xen/arch/arm/include/asm/vgic.h > @@ -355,6 +355,27 @@ extern void vgic_check_inflight_irqs_pending(struct = vcpu *v, > /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. = */ > #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32) > =20 > +static inline unsigned int vgic_def_nr_spis(void) > +{ > +#ifdef CONFIG_GICV3_ESPI > + /* > + * Check if the hardware supports extended SPIs (even if the appropr= iate > + * config is set). If not, the common SPI range will be used. Otherw= ise > + * returns the maximum eSPI INTID, supported by HW GIC, subtracted b= y 32. > + * For non-Dom0 domains, the toolstack or arch_create_domUs function > + * applies the same adjustment to cover local IRQs (please, see comm= ent > + * for macro that is used for regular SPIs - VGIC_DEF_NR_SPIS). We w= ill > + * add back this value during VGIC initialization. This ensures cons= istent > + * handling for Dom0 and other domains. For the regular SPI range in= terrupts > + * in this case, the maximum value of VGIC_DEF_NR_SPIS will be used. > + */ > + if ( gic_number_espis() > 0 ) > + return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32; > +#endif > + > + return VGIC_DEF_NR_SPIS; > +} > + > extern bool vgic_is_valid_line(struct domain *d, unsigned int virq); > =20 > static inline bool vgic_is_spi(struct domain *d, unsigned int virq) --=20 WBR, Volodymyr=