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Wed, 30 Apr 2025 09:48:32 -0400 X-MC-Unique: 9t1_IlpnMES5Gy2AHNDGcA-1 X-Mimecast-MFC-AGG-ID: 9t1_IlpnMES5Gy2AHNDGcA_1746020910 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 0574B1800446; Wed, 30 Apr 2025 13:48:29 +0000 (UTC) Received: from localhost (unknown [10.67.24.156]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 100E919560A3; Wed, 30 Apr 2025 13:48:25 +0000 (UTC) From: Cornelia Huck To: Sebastian Ott Cc: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [PATCH v3 05/10] arm/cpu: accessors for writable id registers In-Reply-To: Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Michael O'Neill, Amy Ross" References: <20250414163849.321857-1-cohuck@redhat.com> <20250414163849.321857-6-cohuck@redhat.com> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Wed, 30 Apr 2025 15:48:19 +0200 Message-ID: <877c31rc9o.fsf@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 On Tue, Apr 29 2025, Sebastian Ott wrote: > On Mon, 14 Apr 2025, Cornelia Huck wrote: >> Also add conversion between the different indices. >> >> Signed-off-by: Cornelia Huck >> --- >> target/arm/cpu.h | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index bbee7ff2414a..775a8aebc5d3 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -876,6 +876,13 @@ typedef struct IdRegMap { >> uint64_t regs[NR_ID_REGS]; >> } IdRegMap; >> >> +#define ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ >> + ({ \ >> + __u64 __op1 = (op1) & 3; \ >> + __op1 -= (__op1 == 3); \ >> + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ >> + }) >> + >> /* REG is ID_XXX */ >> #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ >> ({ \ >> @@ -923,6 +930,17 @@ typedef struct IdRegMap { >> i_->idregs[REG ## _EL1_IDX]; \ >> }) >> >> +#define GET_IDREG_WRITABLE(MAP, REG) \ >> + ({ \ >> + const IdRegMap *m_ = (MAP); \ >> + int index = ARM_FEATURE_ID_RANGE_IDX((sysreg >> 14) & 0x0000c000, \ >> + (sysreg >> 11) & 0x00003800, \ >> + (sysreg >> 7) & 0x00000780, \ >> + (sysreg >> 3) & 0x00000078, \ >> + sysreg & 0x00000007); \ >> + m_->regs[index]; \ >> + }) >> + > > s/sysreg/REG/ > > Also GET_IDREG_WRITABLE doesn't seem to be used in this series. Hm, and it wouldn't have worked if we did use it... probably an artifact left over from earlier refactorings, I think we can get rid of it.