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Wed, 13 Nov 2024 22:03:27 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id jaP9Fi8iNWfPGQAAD6G6ig (envelope-from ); Wed, 13 Nov 2024 22:03:27 +0000 From: Fabiano Rosas To: Ivan Klokov , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, lvivier@redhat.com, pbonzini@redhat.com, Ivan Klokov Subject: Re: [RFC PATCH v6 1/2] target/riscv: Add RISC-V CSR qtest support In-Reply-To: <20241112143826.88130-2-ivan.klokov@syntacore.com> References: <20241112143826.88130-1-ivan.klokov@syntacore.com> <20241112143826.88130-2-ivan.klokov@syntacore.com> Date: Wed, 13 Nov 2024 19:03:25 -0300 Message-ID: <877c96iyfm.fsf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; MISSING_XM_UA(0.00)[]; MIME_TRACE(0.00)[0:+]; TAGGED_RCPT(0.00)[]; RCPT_COUNT_TWELVE(0.00)[12]; RCVD_TLS_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[nongnu.org,dabbelt.com,wdc.com,gmail.com,ventanamicro.com,linux.alibaba.com,redhat.com,syntacore.com]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid] Received-SPF: pass client-ip=2a07:de40:b251:101:10:150:64:2; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Ivan Klokov writes: > The RISC-V architecture supports the creation of custom > CSR-mapped devices. It would be convenient to test them in the same way > as MMIO-mapped devices. To do this, a new call has been added > to read/write CSR registers. > > Signed-off-by: Ivan Klokov > --- > hw/riscv/riscv_hart.c | 55 ++++++++++++++++++++++++++++++++++++++++++ > tests/qtest/libqtest.c | 27 +++++++++++++++++++++ > tests/qtest/libqtest.h | 14 +++++++++++ > 3 files changed, 96 insertions(+) > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index 613ea2aaa0..0b725ff9ce 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -21,6 +21,8 @@ > #include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/module.h" > +#include "qemu/cutils.h" > +#include "sysemu/qtest.h" > #include "sysemu/reset.h" > #include "hw/sysbus.h" > #include "target/riscv/cpu.h" > @@ -42,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) > cpu_reset(CPU(cpu)); > } >=20=20 > +#ifndef CONFIG_USER_ONLY > +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *v= al) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); > + CPURISCVState *env =3D &cpu->env; > + > + int ret =3D RISCV_EXCP_NONE; > + if (strcmp(cmd, "get_csr") =3D=3D 0) { > + ret =3D riscv_csrr(env, csrno, (target_ulong *)val); > + } else if (strcmp(cmd, "set_csr") =3D=3D 0) { > + ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, > + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); > + } > + > + g_assert(ret =3D=3D RISCV_EXCP_NONE); > +} > + > +static bool csr_qtest_callback(CharBackend *chr, gchar **words) > +{ > + if (strcmp(words[0], "csr") =3D=3D 0) { > + > + uint64_t cpu; > + uint64_t val; > + int rc, csr; > + > + rc =3D qemu_strtou64(words[2], NULL, 0, &cpu); > + g_assert(rc =3D=3D 0); > + rc =3D qemu_strtoi(words[3], NULL, 0, &csr); > + g_assert(rc =3D=3D 0); > + rc =3D qemu_strtou64(words[4], NULL, 0, &val); > + g_assert(rc =3D=3D 0); > + csr_call(words[1], cpu, csr, &val); > + > + qtest_send_prefix(chr); > + qtest_sendf(chr, "OK %"PRIx64" "TARGET_FMT_lx"\n", res, (target_= ulong)val); ../hw/riscv/riscv_hart.c: In function =E2=80=98csr_qtest_callback=E2=80=99: ../hw/riscv/riscv_hart.c:81:60: error: =E2=80=98res=E2=80=99 undeclared (fi= rst use in this function) qtest_sendf(chr, "OK %"PRIx64" "TARGET_FMT_lx"\n", res, (target_ul= ong)val); ^~~ compilation terminated due to -Wfatal-errors. I'll leave the rest of the review to the riscv people. Please when you resend add a: Acked-by: Fabiano Rosas > + > + return true; > + } > + > + return false; > +} > + > +static void riscv_cpu_register_csr_qtest_callback(void) > +{ > + static GOnce once; > + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); > +} > +#endif > + > static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, > char *cpu_type, Error **errp) > { > @@ -59,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Err= or **errp) >=20=20 > s->harts =3D g_new0(RISCVCPU, s->num_harts); >=20=20 > +#ifndef CONFIG_USER_ONLY > + riscv_cpu_register_csr_qtest_callback(); > +#endif > + > for (n =3D 0; n < s->num_harts; n++) { > if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { > return; > diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c > index 817fd7aac5..43bfa496e9 100644 > --- a/tests/qtest/libqtest.c > +++ b/tests/qtest/libqtest.c > @@ -1202,6 +1202,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char= *name, > return 0; > } >=20=20 > +static void qtest_rsp_csr(QTestState *s, uint64_t *val) > +{ > + gchar **args; > + uint64_t ret; > + int rc; > + > + args =3D qtest_rsp_args(s, 3); > + > + rc =3D qemu_strtou64(args[1], NULL, 16, &ret); > + g_assert(rc =3D=3D 0); > + rc =3D qemu_strtou64(args[2], NULL, 16, val); > + g_assert(rc =3D=3D 0); > + > + g_strfreev(args); > +} > + > +uint64_t qtest_csr_call(QTestState *s, const char *name, > + uint64_t cpu, int csr, > + uint64_t *val) > +{ > + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", > + name, cpu, csr, *val); > + > + qtest_rsp_csr(s, val); > + return 0; > +} > + > void qtest_add_func(const char *str, void (*fn)(void)) > { > gchar *path =3D g_strdup_printf("/%s/%s", qtest_get_arch(), str); > diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h > index beb96b18eb..b516a16bd4 100644 > --- a/tests/qtest/libqtest.h > +++ b/tests/qtest/libqtest.h > @@ -575,6 +575,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *= name, > uint32_t nargs, uint64_t args, > uint32_t nret, uint64_t ret); >=20=20 > +/** > + * qtest_csr_call: > + * @s: #QTestState instance to operate on. > + * @name: name of the command to call. > + * @cpu: hart number. > + * @csr: CSR number. > + * @val: Value for reading/writing. > + * > + * Call an RISC-V CSR read/write function > + */ > +uint64_t qtest_csr_call(QTestState *s, const char *name, > + uint64_t cpu, int csr, > + unsigned long *val); > + > /** > * qtest_bufread: > * @s: #QTestState instance to operate on.