* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-11-15 13:43 Mitul Golani
2023-11-15 13:43 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.
enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Mitul Golani (3):
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Add Enable/Disable for CMRR based on VRR state
drm/i915: Compute CMRR and calculate vtotal
.../drm/i915/display/intel_crtc_state_dump.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++-
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 126 ++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 10 ++
6 files changed, 178 insertions(+), 20 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers 2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani @ 2023-11-15 13:43 ` Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani 2 siblings, 0 replies; 10+ messages in thread From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ville.syrjala Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 6 +++++ drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++ 4 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 125903007a29..f99d2de840bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; } +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; +} + static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_BOOL(name) do { \ if (current_config->name != pipe_config->name) { \ pipe_config_mismatch(fastset, crtc, __stringify(name), \ @@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.flipline); PIPE_CONF_CHECK_I(vrr.pipeline_full); PIPE_CONF_CHECK_I(vrr.guardband); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_LLI #undef PIPE_CONF_CHECK_BOOL #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE #undef PIPE_CONF_CHECK_P @@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state) || + cmrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9a44350ba05d..e42a0807227b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1406,6 +1406,12 @@ struct intel_crtc_state { u16 flipline, vmin, vmax, guardband; } vrr; + /* Content Match Refresh Rate state */ + struct { + bool enable; + u64 cmrr_n, cmrr_m; + } cmrr; + /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5d905f932cb4..c889b0aa69a4 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); @@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (crtc_state->cmrr.enable) { + crtc_state->cmrr.cmrr_n = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + TRANS_CMRR_N_HI(cpu_transcoder)); + crtc_state->cmrr.cmrr_m = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + TRANS_CMRR_M_HI(cpu_transcoder)); + } + if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 135e8d8dbdf0..06c1e1c47e0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2013,6 +2013,7 @@ #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_CMRR_ENABLE REG_BIT(27) #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) @@ -2089,6 +2090,15 @@ #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define _TRANS_CMRR_M_LO_A 0x604F0 +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A) +#define _TRANS_CMRR_M_HI_A 0x604F4 +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A) +#define _TRANS_CMRR_N_LO_A 0x604F8 +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A) +#define _TRANS_CMRR_N_HI_A 0x604FC +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A) + #define _TRANS_PUSH_A 0x60A70 #define _TRANS_PUSH_B 0x61A70 #define _TRANS_PUSH_C 0x62A70 -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state 2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani @ 2023-11-15 13:43 ` Mitul Golani 2023-11-15 14:23 ` Jani Nikula 2023-11-15 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani 2 siblings, 1 reply; 10+ messages in thread From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ville.syrjala Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- .../drm/i915/display/intel_crtc_state_dump.c | 4 ++- drivers/gpu/drm/i915/display/intel_display.c | 27 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 28 +++++++++++++------ 3 files changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 2d15e82c0b3d..908a4c4ccb00 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_dump_buffer(i915, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_dbg_kms(&i915->drm, + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + str_yes_no(pipe_config->cmrr.enable), str_yes_no(pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f99d2de840bc..ae7cc4eca064 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -937,6 +937,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -946,6 +955,12 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + #undef is_disabling #undef is_enabling @@ -1064,7 +1079,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6754,7 +6770,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6851,9 +6868,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c889b0aa69a4..6da14c18a3e3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } + + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state 2023-11-15 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani @ 2023-11-15 14:23 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2023-11-15 14:23 UTC (permalink / raw) To: Mitul Golani, intel-gfx; +Cc: ville.syrjala On Wed, 15 Nov 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote: > Add CMRR/Fixed Average Vtotal mode enable and disable > functions based on change in VRR mode of operation. > When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal > mode is disabled and vice versa. With this commit setting > the stage for subsequent CMRR enablement. > Where's the patch changelog? > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > .../drm/i915/display/intel_crtc_state_dump.c | 4 ++- > drivers/gpu/drm/i915/display/intel_display.c | 27 +++++++++++++++--- > drivers/gpu/drm/i915/display/intel_vrr.c | 28 +++++++++++++------ > 3 files changed, 46 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > index 2d15e82c0b3d..908a4c4ccb00 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > @@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, > intel_dump_buffer(i915, "ELD: ", pipe_config->eld, > drm_eld_size(pipe_config->eld)); > > - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", > + drm_dbg_kms(&i915->drm, > + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", > + str_yes_no(pipe_config->cmrr.enable), > str_yes_no(pipe_config->vrr.enable), > pipe_config->vrr.vmin, pipe_config->vrr.vmax, > pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f99d2de840bc..ae7cc4eca064 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -937,6 +937,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, > vrr_params_changed(old_crtc_state, new_crtc_state))); > } > > +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ > + if (!new_crtc_state->hw.active) > + return false; > + > + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state); > +} > + > static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, > const struct intel_crtc_state *new_crtc_state) > { > @@ -946,6 +955,12 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, > vrr_params_changed(old_crtc_state, new_crtc_state))); > } > > +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ And the hw.active check here? > + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state); > +} > + > #undef is_disabling > #undef is_enabling > > @@ -1064,7 +1079,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, > intel_atomic_get_new_crtc_state(state, crtc); > enum pipe pipe = crtc->pipe; > > - if (vrr_disabling(old_crtc_state, new_crtc_state)) { > + if (vrr_disabling(old_crtc_state, new_crtc_state) || > + cmrr_disabling(old_crtc_state, new_crtc_state)) { > intel_vrr_disable(old_crtc_state); > intel_crtc_update_active_timings(old_crtc_state, false); > } > @@ -6754,7 +6770,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, > !intel_crtc_needs_modeset(new_crtc_state)) > skl_detach_scalers(new_crtc_state); > > - if (vrr_enabling(old_crtc_state, new_crtc_state)) > + if (vrr_enabling(old_crtc_state, new_crtc_state) || > + cmrr_enabling(old_crtc_state, new_crtc_state)) > intel_vrr_enable(new_crtc_state); > } > > @@ -6851,9 +6868,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, > * FIXME Should be synchronized with the start of vblank somehow... > */ > if (vrr_enabling(old_crtc_state, new_crtc_state) || > - new_crtc_state->update_m_n || new_crtc_state->update_lrr) > + new_crtc_state->update_m_n || new_crtc_state->update_lrr || > + cmrr_enabling(old_crtc_state, new_crtc_state)) > intel_crtc_update_active_timings(new_crtc_state, > - new_crtc_state->vrr.enable); > + new_crtc_state->vrr.enable || > + new_crtc_state->cmrr.enable); > > /* > * We usually enable FIFO underrun interrupts as part of the > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index c889b0aa69a4..6da14c18a3e3 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > - if (!crtc_state->vrr.enable) > + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) > return; > > intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), > @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > - if (!crtc_state->vrr.enable) > + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) > return false; > > return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; > @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > - if (!crtc_state->vrr.enable) > + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && > + crtc_state->cmrr.enable)) > return; > > - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); > - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), > - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); > + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { You already checked that vrr.enable and cmrr.enable can't both be true at the same time. Now you only check vrr.enable here. Yeah, the conditions are bogus. Please don't rush it. > + intel_de_write(dev_priv, > + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); > + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), > + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); > + } > + > + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { Ditto here. > + intel_de_write(dev_priv, > + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); > + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), > + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | > + trans_vrr_ctl(crtc_state)); > + } > } > > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; > > - if (!old_crtc_state->vrr.enable) > + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) > return; > > intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), > @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; > } > > - if (crtc_state->vrr.enable) > + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) > crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > } -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal 2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani @ 2023-11-15 13:43 ` Mitul Golani 2023-11-15 20:30 ` Ville Syrjälä 2 siblings, 1 reply; 10+ messages in thread From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ville.syrjala Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Adaptive Sync Vtotal mode (Legacy VRR) or not. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++++++++-- 3 files changed, 72 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ae7cc4eca064..7e38ac4d6185 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5482,6 +5482,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); + PIPE_CONF_CHECK_BOOL(cmrr.enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 4299cc452e05..66cbc3a6bbe8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -68,6 +68,7 @@ struct drm_printer; #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ BIT(trans)) != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 6da14c18a3e3..ab124e997ef2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -105,6 +105,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); } +static bool +is_cmrr_frac_required(struct intel_crtc_state *crtc_state) +{ + int calculated_refresh_k, actual_refresh_k; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + actual_refresh_k = drm_mode_vrefresh(adjusted_mode) * 1000; + calculated_refresh_k = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal) * 1000; + calculated_refresh_k /= adjusted_mode->crtc_vtotal; + + if (calculated_refresh_k == actual_refresh_k) + return false; + + return true; +} + +static unsigned int +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) +{ + int multiplier_m = 1, multiplier_n = 1, vtotal; + int actual_refresh_rate, desired_refresh_rate; + long long actual_pixel_rate, adjusted_pixel_rate; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + actual_refresh_rate = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal) * 1000; + actual_refresh_rate /= adjusted_mode->crtc_vtotal; + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; + actual_pixel_rate = (actual_pixel_rate * adjusted_mode->crtc_htotal) / 1000; + + if (is_cmrr_frac_required(crtc_state)) { + multiplier_m = 1001; + multiplier_n = 1000; + } + + crtc_state->cmrr.cmrr_n = DIV_ROUND_UP(desired_refresh_rate * + adjusted_mode->crtc_htotal * multiplier_n, multiplier_m) * multiplier_n; + vtotal = DIV_ROUND_UP(actual_pixel_rate * multiplier_n, crtc_state->cmrr.cmrr_n); + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + + return vtotal; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -149,6 +195,22 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; + /* + * When panel is VRR capable and userspace has + * not enabled adaptive sync mode then Fixed Average + * Vtotal mode should be enabled. + */ + if (crtc_state->uapi.vrr_enabled) { + crtc_state->vrr.enable = true; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } else if (HAS_CMRR(i915)) { + crtc_state->cmrr.enable = true; + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } + /* * For XE_LPD+, we use guardband and pipeline override * is deprecated. @@ -161,11 +223,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - crtc_state->framestart_delay - 1); } - - if (crtc_state->uapi.vrr_enabled) { - crtc_state->vrr.enable = true; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } } static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) @@ -292,7 +349,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (HAS_CMRR(dev_priv)) { + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); + } else { + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + } if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n = -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal 2023-11-15 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani @ 2023-11-15 20:30 ` Ville Syrjälä 2023-11-15 21:16 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2023-11-15 20:30 UTC (permalink / raw) To: Mitul Golani; +Cc: jani.nikula, intel-gfx, ville.syrjala On Wed, Nov 15, 2023 at 07:13:26PM +0530, Mitul Golani wrote: > Compute Fixed Average Vtotal/CMRR with resepect to > userspace VRR enablement. Also calculate required > parameters in case of CMRR is enabled. During > intel_vrr_compute_config, CMRR is getting enabled > based on userspace has enabled Adaptive Sync Vtotal > mode (Legacy VRR) or not. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > .../drm/i915/display/intel_display_device.h | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++++++++-- > 3 files changed, 72 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index ae7cc4eca064..7e38ac4d6185 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5482,6 +5482,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(vrr.guardband); > PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); > PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); > + PIPE_CONF_CHECK_BOOL(cmrr.enable); > } > > #undef PIPE_CONF_CHECK_X > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 4299cc452e05..66cbc3a6bbe8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -68,6 +68,7 @@ struct drm_printer; > #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ > BIT(trans)) != 0) > #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) > +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) > #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) > #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) > #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 6da14c18a3e3..ab124e997ef2 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -105,6 +105,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) > return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); > } > > +static bool > +is_cmrr_frac_required(struct intel_crtc_state *crtc_state) > +{ > + int calculated_refresh_k, actual_refresh_k; > + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; > + > + actual_refresh_k = drm_mode_vrefresh(adjusted_mode) * 1000; > + calculated_refresh_k = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, > + adjusted_mode->crtc_htotal) * 1000; > + calculated_refresh_k /= adjusted_mode->crtc_vtotal; > + > + if (calculated_refresh_k == actual_refresh_k) > + return false; > + > + return true; > +} > + > +static unsigned int > +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) > +{ > + int multiplier_m = 1, multiplier_n = 1, vtotal; > + int actual_refresh_rate, desired_refresh_rate; > + long long actual_pixel_rate, adjusted_pixel_rate; > + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; > + > + actual_refresh_rate = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, > + adjusted_mode->crtc_htotal) * 1000; > + actual_refresh_rate /= adjusted_mode->crtc_vtotal; > + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); The actual refresh rate is the desired refresh rate. None of this stuff makes any sense. > + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; > + actual_pixel_rate = (actual_pixel_rate * adjusted_mode->crtc_htotal) / 1000; > + > + if (is_cmrr_frac_required(crtc_state)) { > + multiplier_m = 1001; > + multiplier_n = 1000; > + } > + > + crtc_state->cmrr.cmrr_n = DIV_ROUND_UP(desired_refresh_rate * > + adjusted_mode->crtc_htotal * multiplier_n, multiplier_m) * multiplier_n; > + vtotal = DIV_ROUND_UP(actual_pixel_rate * multiplier_n, crtc_state->cmrr.cmrr_n); > + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; > + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); > + > + return vtotal; > +} > + > void > intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > @@ -149,6 +195,22 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; > > + /* > + * When panel is VRR capable and userspace has > + * not enabled adaptive sync mode then Fixed Average > + * Vtotal mode should be enabled. > + */ > + if (crtc_state->uapi.vrr_enabled) { > + crtc_state->vrr.enable = true; > + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > + } else if (HAS_CMRR(i915)) { > + crtc_state->cmrr.enable = true; > + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); > + crtc_state->vrr.vmin = crtc_state->vrr.vmax; > + crtc_state->vrr.flipline = crtc_state->vrr.vmin; > + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > + } > + > /* > * For XE_LPD+, we use guardband and pipeline override > * is deprecated. > @@ -161,11 +223,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - > crtc_state->framestart_delay - 1); > } > - > - if (crtc_state->uapi.vrr_enabled) { > - crtc_state->vrr.enable = true; > - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > - } > } > > static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) > @@ -292,7 +349,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > > trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); > > - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > + if (HAS_CMRR(dev_priv)) { > + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && > + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); > + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && > + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); > + } else { > + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > + } > > if (crtc_state->cmrr.enable) { > crtc_state->cmrr.cmrr_n = > -- > 2.25.1 -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal 2023-11-15 20:30 ` Ville Syrjälä @ 2023-11-15 21:16 ` Ville Syrjälä 0 siblings, 0 replies; 10+ messages in thread From: Ville Syrjälä @ 2023-11-15 21:16 UTC (permalink / raw) To: Mitul Golani; +Cc: jani.nikula, intel-gfx, ville.syrjala On Wed, Nov 15, 2023 at 10:30:11PM +0200, Ville Syrjälä wrote: > On Wed, Nov 15, 2023 at 07:13:26PM +0530, Mitul Golani wrote: > > Compute Fixed Average Vtotal/CMRR with resepect to > > userspace VRR enablement. Also calculate required > > parameters in case of CMRR is enabled. During > > intel_vrr_compute_config, CMRR is getting enabled > > based on userspace has enabled Adaptive Sync Vtotal > > mode (Legacy VRR) or not. > > > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > .../drm/i915/display/intel_display_device.h | 1 + > > drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++++++++-- > > 3 files changed, 72 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ae7cc4eca064..7e38ac4d6185 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -5482,6 +5482,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > > PIPE_CONF_CHECK_I(vrr.guardband); > > PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); > > PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); > > + PIPE_CONF_CHECK_BOOL(cmrr.enable); > > } > > > > #undef PIPE_CONF_CHECK_X > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > > index 4299cc452e05..66cbc3a6bbe8 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > > @@ -68,6 +68,7 @@ struct drm_printer; > > #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ > > BIT(trans)) != 0) > > #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) > > +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) > > #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) > > #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) > > #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > > index 6da14c18a3e3..ab124e997ef2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > > @@ -105,6 +105,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) > > return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); > > } > > > > +static bool > > +is_cmrr_frac_required(struct intel_crtc_state *crtc_state) > > +{ > > + int calculated_refresh_k, actual_refresh_k; > > + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; > > + > > + actual_refresh_k = drm_mode_vrefresh(adjusted_mode) * 1000; > > + calculated_refresh_k = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, > > + adjusted_mode->crtc_htotal) * 1000; > > + calculated_refresh_k /= adjusted_mode->crtc_vtotal; > > + > > + if (calculated_refresh_k == actual_refresh_k) > > + return false; > > + > > + return true; > > +} > > + > > +static unsigned int > > +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) > > +{ > > + int multiplier_m = 1, multiplier_n = 1, vtotal; > > + int actual_refresh_rate, desired_refresh_rate; > > + long long actual_pixel_rate, adjusted_pixel_rate; > > + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; > > + > > + actual_refresh_rate = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, > > + adjusted_mode->crtc_htotal) * 1000; > > + actual_refresh_rate /= adjusted_mode->crtc_vtotal; > > + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); > > The actual refresh rate is the desired refresh rate. None of this > stuff makes any sense. Just to elaborate a bit more, there is no mechanism in the uapi to specify refresh rate and dotclock independently, so we have no use for CMRR without some kind of new uapi. Hmm. I suppose one slight exception might be eDP where we pick the dotclock from the set of fixed modes, and thus we try to extend the vblank to achieve the target refresh rate with a fixed dotclock. So perhaps CMRR could be used there to achieve a slightly more accurate average refresh rate. But there are a lot of details to think about since the frame timings would change semi-randomly so all the vblank timing stuff might get a lot more complicated. > > > + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; > > + actual_pixel_rate = (actual_pixel_rate * adjusted_mode->crtc_htotal) / 1000; > > + > > + if (is_cmrr_frac_required(crtc_state)) { > > + multiplier_m = 1001; > > + multiplier_n = 1000; > > + } > > + > > + crtc_state->cmrr.cmrr_n = DIV_ROUND_UP(desired_refresh_rate * > > + adjusted_mode->crtc_htotal * multiplier_n, multiplier_m) * multiplier_n; > > + vtotal = DIV_ROUND_UP(actual_pixel_rate * multiplier_n, crtc_state->cmrr.cmrr_n); > > + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; > > + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); > > + > > + return vtotal; > > +} > > + > > void > > intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > struct drm_connector_state *conn_state) > > @@ -149,6 +195,22 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > > > crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; > > > > + /* > > + * When panel is VRR capable and userspace has > > + * not enabled adaptive sync mode then Fixed Average > > + * Vtotal mode should be enabled. > > + */ > > + if (crtc_state->uapi.vrr_enabled) { > > + crtc_state->vrr.enable = true; > > + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > > + } else if (HAS_CMRR(i915)) { > > + crtc_state->cmrr.enable = true; > > + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); > > + crtc_state->vrr.vmin = crtc_state->vrr.vmax; > > + crtc_state->vrr.flipline = crtc_state->vrr.vmin; > > + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > > + } > > + > > /* > > * For XE_LPD+, we use guardband and pipeline override > > * is deprecated. > > @@ -161,11 +223,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - > > crtc_state->framestart_delay - 1); > > } > > - > > - if (crtc_state->uapi.vrr_enabled) { > > - crtc_state->vrr.enable = true; > > - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > > - } > > } > > > > static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) > > @@ -292,7 +349,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > > > > trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); > > > > - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > > + if (HAS_CMRR(dev_priv)) { > > + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && > > + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); > > + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && > > + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); > > + } else { > > + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > > + } > > > > if (crtc_state->cmrr.enable) { > > crtc_state->cmrr.cmrr_n = > > -- > > 2.25.1 > > -- > Ville Syrjälä > Intel -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support @ 2023-11-21 17:35 Mitul Golani 2023-11-21 17:35 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 0 siblings, 1 reply; 10+ messages in thread From: Mitul Golani @ 2023-11-21 17:35 UTC (permalink / raw) To: intel-gfx CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. Mitul Golani (3): drm/i915: Define and compute Transcoder CMRR registers drm/i915: Add Enable/Disable for CMRR based on VRR state drm/i915: Compute CMRR and calculate vtotal .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_vrr.c | 126 ++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 6 files changed, 181 insertions(+), 20 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state 2023-11-21 17:35 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani @ 2023-11-21 17:35 ` Mitul Golani 0 siblings, 0 replies; 10+ messages in thread From: Mitul Golani @ 2023-11-21 17:35 UTC (permalink / raw) To: intel-gfx Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling. (Similar to enable case).[Jani] - Correct messed up condition in intel_vrr_enable while fixing rev2. [Jani] --v4: - Removing RFC tag. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- .../drm/i915/display/intel_crtc_state_dump.c | 4 ++- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++----- 3 files changed, 49 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 2d15e82c0b3d..908a4c4ccb00 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_dump_buffer(i915, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_dbg_kms(&i915->drm, + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + str_yes_no(pipe_config->cmrr.enable), str_yes_no(pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ea545414109e..5bb36cadd44a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -936,6 +936,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -945,6 +954,15 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->hw.active) + return false; + + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + #undef is_disabling #undef is_enabling @@ -1063,7 +1081,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6583,7 +6602,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6680,9 +6700,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c889b0aa69a4..8f1d241e1f79 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->vrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } + + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support @ 2023-11-22 6:59 Mitul Golani 2023-11-22 6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 0 siblings, 1 reply; 10+ messages in thread From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw) To: intel-gfx CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. Mitul Golani (3): drm/i915: Define and compute Transcoder CMRR registers drm/i915: Add Enable/Disable for CMRR based on VRR state drm/i915: Compute CMRR and calculate vtotal .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_vrr.c | 129 ++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 6 files changed, 184 insertions(+), 20 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state 2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani @ 2023-11-22 6:59 ` Mitul Golani 0 siblings, 0 replies; 10+ messages in thread From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw) To: intel-gfx Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling. (Similar to enable case).[Jani] - Correct messed up condition in intel_vrr_enable while fixing rev2. [Jani] --v4: - Removing RFC tag. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- .../drm/i915/display/intel_crtc_state_dump.c | 4 ++- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++----- 3 files changed, 49 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 2d15e82c0b3d..908a4c4ccb00 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_dump_buffer(i915, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_dbg_kms(&i915->drm, + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + str_yes_no(pipe_config->cmrr.enable), str_yes_no(pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cae399a6c54d..d54b629c5379 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -936,6 +936,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -945,6 +954,15 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->hw.active) + return false; + + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + #undef is_disabling #undef is_enabling @@ -1063,7 +1081,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6558,7 +6577,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6655,9 +6675,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c889b0aa69a4..8f1d241e1f79 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->vrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } + + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 0/3] Implement CMRR Support @ 2023-12-05 18:36 Mitul Golani 2023-12-05 18:36 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 0 siblings, 1 reply; 10+ messages in thread From: Mitul Golani @ 2023-12-05 18:36 UTC (permalink / raw) To: intel-gfx CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. --v6: - CMRR handling in co-existatnce of LRR and DRRS - Correct vtotal paramas accuracy and add 2 digit precision. Mitul Golani (3): drm/i915: Define and compute Transcoder CMRR registers drm/i915: Add Enable/Disable for CMRR based on VRR state drm/i915: Compute CMRR and calculate vtotal .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 61 +++++++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_vrr.c | 136 ++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 6 files changed, 197 insertions(+), 21 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state 2023-12-05 18:36 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani @ 2023-12-05 18:36 ` Mitul Golani 0 siblings, 0 replies; 10+ messages in thread From: Mitul Golani @ 2023-12-05 18:36 UTC (permalink / raw) To: intel-gfx Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 37 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++---- 3 files changed, 55 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 49fd100ec98a..cb0e17ec2d01 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -308,7 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_dump_buffer(i915, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_dbg_kms(&i915->drm, + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + str_yes_no(pipe_config->cmrr.enable), str_yes_no(pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 62dd8513a07a..e7382d2855ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -985,6 +985,18 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) || + (new_crtc_state->cmrr.enable && + (new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_params_changed(old_crtc_state, new_crtc_state))); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -997,6 +1009,18 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->hw.active) + return false; + + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) || + (old_crtc_state->cmrr.enable && + (new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_params_changed(old_crtc_state, new_crtc_state))); +} + static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -1018,7 +1042,6 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, (old_crtc_state->has_audio && memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); } - #undef is_disabling #undef is_enabling @@ -1140,7 +1163,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6630,7 +6654,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6727,9 +6752,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c889b0aa69a4..8f1d241e1f79 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->vrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } + + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-12-05 18:41 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani 2023-11-15 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 2023-11-15 14:23 ` Jani Nikula 2023-11-15 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani 2023-11-15 20:30 ` Ville Syrjälä 2023-11-15 21:16 ` Ville Syrjälä -- strict thread matches above, loose matches on Subject: below -- 2023-11-21 17:35 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-11-21 17:35 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-11-22 6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani 2023-12-05 18:36 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani 2023-12-05 18:36 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
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