From: Jani Nikula <jani.nikula@linux.intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>,
intel-xe@lists.freedesktop.org
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P
Date: Mon, 29 May 2023 11:01:42 +0300 [thread overview]
Message-ID: <877csrin15.fsf@intel.com> (raw)
In-Reply-To: <20230526211730.2774851-3-anusha.srivatsa@intel.com>
On Fri, 26 May 2023, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> Refer to platform with the same consistent name.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Send this first to intel-gfx, get it merged to i915, and then
cherry-pick -x backport it to xe.
Otherwise, please avoid i915 changes in the xe branch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_step.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f6223d8f13b8..bb0d8cd7034e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3409,7 +3409,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> - else if (IS_ADLP_RPLU(dev_priv))
> + else if (IS_ALDERLAKE_P_RPLU(dev_priv))
> dev_priv->display.cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14c5338c96a6..e870dd412a75 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -578,7 +578,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_N(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> -#define IS_ADLP_RPLP(i915) \
> +#define IS_ALDERLAKE_P_RPLU(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_ADLP_RPLU(i915) \
> IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 84a6fe736a3b..6a8816fbc15a 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -191,7 +191,7 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ADLP_N(i915)) {
> revids = adlp_n_revids;
> size = ARRAY_SIZE(adlp_n_revids);
> - } else if (IS_ADLP_RPLP(i915)) {
> + } else if (IS_ALDERLAKE_P_RPLU(i915)) {
> revids = adlp_rplp_revids;
> size = ARRAY_SIZE(adlp_rplp_revids);
> } else if (IS_ALDERLAKE_P(i915)) {
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-05-29 8:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 21:17 [Intel-xe] [PATCH 0/5] RPLS and other minor support Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 1/5] drm/xe/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
2023-05-29 8:00 ` Jani Nikula
2023-05-26 21:17 ` [Intel-xe] [PATCH 2/5] drm/i915/adlp: s/ADLP/ALDERLAKE_P Anusha Srivatsa
2023-05-29 8:01 ` Jani Nikula [this message]
2023-05-26 21:17 ` [Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 4/5] drm/xe/rpls: Add Stepping info for RPLS Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] [PATCH 5/5] drm/xe: Add missing ADL entries to xe_test_wa Anusha Srivatsa
2023-05-26 21:17 ` [Intel-xe] ✓ CI.Patch_applied: success for RPLS and other minor support (rev2) Patchwork
2023-05-26 21:18 ` [Intel-xe] ✗ CI.KUnit: failure " Patchwork
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