From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E9A6C4332F for ; Wed, 2 Nov 2022 06:17:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8322310E0C0; Wed, 2 Nov 2022 06:17:38 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7792010E0B7; Wed, 2 Nov 2022 06:17:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667369852; x=1698905852; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=+pVJKXPEeuK5YsGjiyLZQ33jXQXaxSddZtw60G79SwY=; b=btX0DnURerud+qVfi94MhO4FX2x5vKomh4V3QW1qXZmXYYo8HGP8CQpQ 4BVDscrpaVSQs7c8AyqfeF3x3Xo1bEf0W78teXJz8xgA6+xWesDTP2AUn Ud/DWP1+KuHhUjDItkOkGoX2+8s3Wk+ZZxw+jn/mjl1Sz1WPpYhJqpvRd s+/0ZXmArKu37rlnlkVlifOimJjkn6bqqsz9/t34f1zHC+B1WabY7w+vM WO9JLMhKx3fWM9GAlY40NYHeA6KoNFHKGcvaWiNFARErwrxOljBTHZ8FZ nah8gJRWb6d7pi2Uy/l4Li5NIFXZLlcQsdXlV2+jeSCwoLNJTEtu9jE9N w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="373546614" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="373546614" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="634137452" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="634137452" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.112.245]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 Date: Tue, 01 Nov 2022 23:17:31 -0700 Message-ID: <877d0dnamc.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jani Nikula In-Reply-To: <87cza77xh6.fsf@intel.com> References: <20221031172655.606165-1-ashutosh.dixit@intel.com> <87cza77xh6.fsf@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Don't use FIELD_PREP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti , intel-gfx@lists.freedesktop.org, llvm@lists.linux.dev, ndesaulniers@google.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 01 Nov 2022 03:58:13 -0700, Jani Nikula wrote: > > On Mon, 31 Oct 2022, Ashutosh Dixit wrote: > > FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant > > mask. When the mask comes in as the argument of a function these checks can > > can fail depending on the compiler (gcc vs clang), optimization level, > > etc. Use a simpler version of FIELD_PREP which skips these checks. The > > checks are not needed because the mask is formed using REG_GENMASK (so is > > actually a compile time constant). > > > > v2: Split REG_FIELD_PREP into a macro with checks and one without and use > > the one without checks in i915_hwmon.c (Gwan-gyeong Mun) > > I frankly think you're solving the wrong problem here. See [1]. We can consider the sort of refactoring suggested in [1] in the future, right now I thought I'll offer what in my opinion is the correct way to fix the clang compile break incrementally with the current code. But otherwise feel free to go with whatever you think is the correct course of action for this issue. Even if we don't fix the issue the clang guys will (as they have in the past). Thanks. -- Ashutosh > [1] https://lore.kernel.org/r/87leov7yix.fsf@intel.com > > > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7354 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/i915_hwmon.c | 2 +- > > drivers/gpu/drm/i915/i915_reg_defs.h | 17 +++++++++++------ > > 2 files changed, 12 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > index 9e97814930254..ae435b035229a 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > @@ -112,7 +112,7 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr, > > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); > > > > bits_to_clear = field_msk; > > - bits_to_set = FIELD_PREP(field_msk, nval); > > + bits_to_set = __REG_FIELD_PREP(field_msk, nval); > > > > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr, > > bits_to_clear, bits_to_set); > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h > > index f1859046a9c48..dddacc8d48928 100644 > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > > @@ -67,12 +67,17 @@ > > * > > * @return: @__val masked and shifted into the field defined by @__mask. > > */ > > -#define REG_FIELD_PREP(__mask, __val) \ > > - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ > > - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) > > +#define __REG_FIELD_PREP_CHK(__mask, __val) \ > > + (BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))) > > + > > +#define __REG_FIELD_PREP(__mask, __val) \ > > + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)))) > > + > > +#define REG_FIELD_PREP(__mask, __val) \ > > + (__REG_FIELD_PREP(__mask, __val) + __REG_FIELD_PREP_CHK(__mask, __val)) > > > > /** > > * REG_FIELD_GET() - Extract a u32 bitfield value From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8356D7B for ; Wed, 2 Nov 2022 06:17:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667369852; x=1698905852; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=+pVJKXPEeuK5YsGjiyLZQ33jXQXaxSddZtw60G79SwY=; b=btX0DnURerud+qVfi94MhO4FX2x5vKomh4V3QW1qXZmXYYo8HGP8CQpQ 4BVDscrpaVSQs7c8AyqfeF3x3Xo1bEf0W78teXJz8xgA6+xWesDTP2AUn Ud/DWP1+KuHhUjDItkOkGoX2+8s3Wk+ZZxw+jn/mjl1Sz1WPpYhJqpvRd s+/0ZXmArKu37rlnlkVlifOimJjkn6bqqsz9/t34f1zHC+B1WabY7w+vM WO9JLMhKx3fWM9GAlY40NYHeA6KoNFHKGcvaWiNFARErwrxOljBTHZ8FZ nah8gJRWb6d7pi2Uy/l4Li5NIFXZLlcQsdXlV2+jeSCwoLNJTEtu9jE9N w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="371412679" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="371412679" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="634137452" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="634137452" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.112.245]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 Date: Tue, 01 Nov 2022 23:17:31 -0700 Message-ID: <877d0dnamc.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jani Nikula Cc: , , , Andi Shyti , , Subject: Re: [PATCH] drm/i915/hwmon: Don't use FIELD_PREP In-Reply-To: <87cza77xh6.fsf@intel.com> References: <20221031172655.606165-1-ashutosh.dixit@intel.com> <87cza77xh6.fsf@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII On Tue, 01 Nov 2022 03:58:13 -0700, Jani Nikula wrote: > > On Mon, 31 Oct 2022, Ashutosh Dixit wrote: > > FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant > > mask. When the mask comes in as the argument of a function these checks can > > can fail depending on the compiler (gcc vs clang), optimization level, > > etc. Use a simpler version of FIELD_PREP which skips these checks. The > > checks are not needed because the mask is formed using REG_GENMASK (so is > > actually a compile time constant). > > > > v2: Split REG_FIELD_PREP into a macro with checks and one without and use > > the one without checks in i915_hwmon.c (Gwan-gyeong Mun) > > I frankly think you're solving the wrong problem here. See [1]. We can consider the sort of refactoring suggested in [1] in the future, right now I thought I'll offer what in my opinion is the correct way to fix the clang compile break incrementally with the current code. But otherwise feel free to go with whatever you think is the correct course of action for this issue. Even if we don't fix the issue the clang guys will (as they have in the past). Thanks. -- Ashutosh > [1] https://lore.kernel.org/r/87leov7yix.fsf@intel.com > > > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7354 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/i915_hwmon.c | 2 +- > > drivers/gpu/drm/i915/i915_reg_defs.h | 17 +++++++++++------ > > 2 files changed, 12 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > index 9e97814930254..ae435b035229a 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > @@ -112,7 +112,7 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr, > > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); > > > > bits_to_clear = field_msk; > > - bits_to_set = FIELD_PREP(field_msk, nval); > > + bits_to_set = __REG_FIELD_PREP(field_msk, nval); > > > > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr, > > bits_to_clear, bits_to_set); > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h > > index f1859046a9c48..dddacc8d48928 100644 > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > > @@ -67,12 +67,17 @@ > > * > > * @return: @__val masked and shifted into the field defined by @__mask. > > */ > > -#define REG_FIELD_PREP(__mask, __val) \ > > - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ > > - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) > > +#define __REG_FIELD_PREP_CHK(__mask, __val) \ > > + (BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))) > > + > > +#define __REG_FIELD_PREP(__mask, __val) \ > > + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)))) > > + > > +#define REG_FIELD_PREP(__mask, __val) \ > > + (__REG_FIELD_PREP(__mask, __val) + __REG_FIELD_PREP_CHK(__mask, __val)) > > > > /** > > * REG_FIELD_GET() - Extract a u32 bitfield value From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E4E6C433FE for ; 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a="373546614" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="373546614" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="634137452" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="634137452" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.112.245]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 23:17:31 -0700 Date: Tue, 01 Nov 2022 23:17:31 -0700 Message-ID: <877d0dnamc.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jani Nikula Subject: Re: [PATCH] drm/i915/hwmon: Don't use FIELD_PREP In-Reply-To: <87cza77xh6.fsf@intel.com> References: <20221031172655.606165-1-ashutosh.dixit@intel.com> <87cza77xh6.fsf@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti , intel-gfx@lists.freedesktop.org, llvm@lists.linux.dev, ndesaulniers@google.com, dri-devel@lists.freedesktop.org, gwan-gyeong.mun@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, 01 Nov 2022 03:58:13 -0700, Jani Nikula wrote: > > On Mon, 31 Oct 2022, Ashutosh Dixit wrote: > > FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant > > mask. When the mask comes in as the argument of a function these checks can > > can fail depending on the compiler (gcc vs clang), optimization level, > > etc. Use a simpler version of FIELD_PREP which skips these checks. The > > checks are not needed because the mask is formed using REG_GENMASK (so is > > actually a compile time constant). > > > > v2: Split REG_FIELD_PREP into a macro with checks and one without and use > > the one without checks in i915_hwmon.c (Gwan-gyeong Mun) > > I frankly think you're solving the wrong problem here. See [1]. We can consider the sort of refactoring suggested in [1] in the future, right now I thought I'll offer what in my opinion is the correct way to fix the clang compile break incrementally with the current code. But otherwise feel free to go with whatever you think is the correct course of action for this issue. Even if we don't fix the issue the clang guys will (as they have in the past). Thanks. -- Ashutosh > [1] https://lore.kernel.org/r/87leov7yix.fsf@intel.com > > > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7354 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/i915_hwmon.c | 2 +- > > drivers/gpu/drm/i915/i915_reg_defs.h | 17 +++++++++++------ > > 2 files changed, 12 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > index 9e97814930254..ae435b035229a 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > @@ -112,7 +112,7 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr, > > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); > > > > bits_to_clear = field_msk; > > - bits_to_set = FIELD_PREP(field_msk, nval); > > + bits_to_set = __REG_FIELD_PREP(field_msk, nval); > > > > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr, > > bits_to_clear, bits_to_set); > > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h > > index f1859046a9c48..dddacc8d48928 100644 > > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > > @@ -67,12 +67,17 @@ > > * > > * @return: @__val masked and shifted into the field defined by @__mask. > > */ > > -#define REG_FIELD_PREP(__mask, __val) \ > > - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ > > - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) > > +#define __REG_FIELD_PREP_CHK(__mask, __val) \ > > + (BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ > > + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ > > + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ > > + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))) > > + > > +#define __REG_FIELD_PREP(__mask, __val) \ > > + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)))) > > + > > +#define REG_FIELD_PREP(__mask, __val) \ > > + (__REG_FIELD_PREP(__mask, __val) + __REG_FIELD_PREP_CHK(__mask, __val)) > > > > /** > > * REG_FIELD_GET() - Extract a u32 bitfield value