From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF373C433FE for ; Thu, 6 Jan 2022 16:27:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241236AbiAFQ1x (ORCPT ); Thu, 6 Jan 2022 11:27:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241226AbiAFQ1u (ORCPT ); Thu, 6 Jan 2022 11:27:50 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D836BC061245; Thu, 6 Jan 2022 08:27:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9201CB82295; Thu, 6 Jan 2022 16:27:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23D63C36AEB; Thu, 6 Jan 2022 16:27:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641486467; bh=k2zDKR7HVZqgDJoRzwQ+fwXeBgpmIl0hRM0018L7Ccc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=UdjxTnc/lru+ZrGJ7DIhSwYusrtzOxwwp+IUVU3R3Hl66WEV5Ogs3hvpZtmNOs0ts O6R49AXdZv7cH99isBGBYa4UeZSErXvxbF6/osO0ycElY0iHvINvodw0396nj69t41 t0zysYUXb5SCgIvVOAo7lgBN3fB0ifYnPRDUfuR96Gb7bTE4yoTSHPAYkXC1lpV4SZ wTumHl81DH7rcFzAg55W7eb1r08nmKCbsQOaSfMyu/oNNKPNA2IpHXL0c4+VzXY6Ky 3CfPBZoQtnGcJiieYDFBG0d6ZpqGlEGErQdKhkKwiOkFtBxLlUczGkb3jwdcrpSaFZ biIbXdRaZIfRA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n5Vc9-00GO89-6j; Thu, 06 Jan 2022 16:27:45 +0000 Date: Thu, 06 Jan 2022 16:27:44 +0000 Message-ID: <877dbcvngf.wl-maz@kernel.org> From: Marc Zyngier To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Marek =?UTF-8?B?QmVow7pu?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts In-Reply-To: <20220106162047.vqykmygs75eimfgy@pali> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> <878rvsvoyo.wl-maz@kernel.org> <20220106162047.vqykmygs75eimfgy@pali> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pali@kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, thomas.petazzoni@bootlin.com, kw@linux.com, kabel@kernel.org, rmk+kernel@armlinux.org.uk, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, 06 Jan 2022 16:20:47 +0000, Pali Roh=C3=A1r wrote: >=20 > On Thursday 06 January 2022 15:55:11 Marc Zyngier wrote: > > On Thu, 06 Jan 2022 15:44:47 +0000, > > Pali Roh=C3=A1r wrote: > > >=20 > > > On Thursday 06 January 2022 15:28:20 Marc Zyngier wrote: > > > > On Wed, 05 Jan 2022 15:02:38 +0000, > > > > Pali Roh=C3=A1r wrote: > > > > >=20 > > > > > This adds support for legacy INTx interrupts received from other = PCIe > > > > > devices and which are reported by a new INTx irq chip. > > > > >=20 > > > > > With this change, kernel can distinguish between INTA, INTB, INTC= and INTD > > > > > interrupts. > > > > >=20 > > > > > Note that for this support, device tree files has to be properly = adjusted > > > > > to provide "interrupts" or "interrupts-extended" property with in= tx > > > > > interrupt source, "interrupt-names" property with "intx" string a= nd also > > > > > 'interrupt-controller' subnode must be defined. > > > > >=20 > > > > > If device tree files do not provide these nodes then driver would= work as > > > > > before. > > > > >=20 > > > > > Signed-off-by: Pali Roh=C3=A1r > > > > > --- > > > > > drivers/pci/controller/pci-mvebu.c | 182 +++++++++++++++++++++++= ++++-- > > > > > 1 file changed, 174 insertions(+), 8 deletions(-) > > > > >=20 > > > > > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/con= troller/pci-mvebu.c > > > > > index 1e90ab888075..04bcdd7b7a6d 100644 > > > > > --- a/drivers/pci/controller/pci-mvebu.c > > > > > +++ b/drivers/pci/controller/pci-mvebu.c > > > > > @@ -54,9 +54,10 @@ > > > > > PCIE_CONF_ADDR_EN) > > > > > #define PCIE_CONF_DATA_OFF 0x18fc > > > > > #define PCIE_INT_CAUSE_OFF 0x1900 > > > > > +#define PCIE_INT_UNMASK_OFF 0x1910 > > > > > +#define PCIE_INT_INTX(i) BIT(24+i) > > > > > #define PCIE_INT_PM_PME BIT(28) > > > > > -#define PCIE_MASK_OFF 0x1910 > > > > > -#define PCIE_MASK_ENABLE_INTS 0x0f000000 > > > > > +#define PCIE_INT_ALL_MASK GENMASK(31, 0) > > > > > #define PCIE_CTRL_OFF 0x1a00 > > > > > #define PCIE_CTRL_X1_MODE 0x0001 > > > > > #define PCIE_CTRL_RC_MODE BIT(1) > > > > > @@ -110,6 +111,10 @@ struct mvebu_pcie_port { > > > > > struct mvebu_pcie_window iowin; > > > > > u32 saved_pcie_stat; > > > > > struct resource regs; > > > > > + struct irq_domain *intx_irq_domain; > > > > > + struct irq_chip intx_irq_chip; > > > >=20 > > > > Why is this structure per port? It really should be global. Printing > > > > the port number in the name isn't enough of a reason. > > >=20 > > > Because each port has its own independent set of INTA-INTD > > > interrupts. > >=20 > > That doesn't warrant a copy of an irq_chip structure that contains the > > exact same callbacks, and only differs by *a string*. And the use of > > this string is only to end-up in /proc/interrupts, which is totally > > pointless. > >=20 > > >=20 > > > > > + raw_spinlock_t irq_lock; > > > > > + int intx_irq; > > > > > }; > > > > > =20 > > > > > static inline void mvebu_writel(struct mvebu_pcie_port *port, u3= 2 val, u32 reg) > > > > > @@ -235,7 +240,7 @@ static void mvebu_pcie_setup_wins(struct mveb= u_pcie_port *port) > > > > > =20 > > > > > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > > > > > { > > > > > - u32 ctrl, lnkcap, cmd, dev_rev, mask; > > > > > + u32 ctrl, lnkcap, cmd, dev_rev, unmask; > > > > > =20 > > > > > /* Setup PCIe controller to Root Complex mode. */ > > > > > ctrl =3D mvebu_readl(port, PCIE_CTRL_OFF); > > > > > @@ -288,10 +293,30 @@ static void mvebu_pcie_setup_hw(struct mveb= u_pcie_port *port) > > > > > /* Point PCIe unit MBUS decode windows to DRAM space. */ > > > > > mvebu_pcie_setup_wins(port); > > > > > =20 > > > > > - /* Enable interrupt lines A-D. */ > > > > > - mask =3D mvebu_readl(port, PCIE_MASK_OFF); > > > > > - mask |=3D PCIE_MASK_ENABLE_INTS; > > > > > - mvebu_writel(port, mask, PCIE_MASK_OFF); > > > > > + /* Mask all interrupt sources. */ > > > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); > > > > > + > > > > > + /* Clear all interrupt causes. */ > > > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); > > > > > + > > > > > + if (port->intx_irq <=3D 0) { > > > > > + /* > > > > > + * When neither "summary" interrupt, nor "intx" interrupt was > > > > > + * specified in DT then unmask all legacy INTx interrupts as in > > > > > + * this case driver does not provide a way for masking and > > > > > + * unmasking of individual legacy INTx interrupts. In this case > > > > > + * all interrupts, including legacy INTx are reported via one > > > > > + * shared GIC source and therefore kernel cannot distinguish > > > > > + * which individual legacy INTx was triggered. These interrupts > > > > > + * are shared, so it should not cause any issue. Just > > > > > + * performance penalty as every PCIe interrupt handler needs to > > > > > + * be called when some interrupt is triggered. > > > > > + */ > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > + unmask |=3D PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | > > > > > + PCIE_INT_INTX(2) | PCIE_INT_INTX(3); > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > >=20 > > > > Maybe worth printing a warning here, so that the user knows they are > > > > on thin ice. > > >=20 > > > Ok. I can add it here. Anyway, this is default current state without > > > this patch. > > >=20 > > > > > + } > > > > > } > > > > > =20 > > > > > static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu= _pcie *pcie, > > > > > @@ -924,6 +949,109 @@ static struct pci_ops mvebu_pcie_ops =3D { > > > > > .write =3D mvebu_pcie_wr_conf, > > > > > }; > > > > > =20 > > > > > +static void mvebu_pcie_intx_irq_mask(struct irq_data *d) > > > > > +{ > > > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > > > + unsigned long flags; > > > > > + u32 unmask; > > > > > + > > > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > + unmask &=3D ~PCIE_INT_INTX(hwirq); > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > > > +} > > > > > + > > > > > +static void mvebu_pcie_intx_irq_unmask(struct irq_data *d) > > > > > +{ > > > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > > > + unsigned long flags; > > > > > + u32 unmask; > > > > > + > > > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > + unmask |=3D PCIE_INT_INTX(hwirq); > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > > > +} > > > > > + > > > > > +static int mvebu_pcie_intx_irq_map(struct irq_domain *h, > > > > > + unsigned int virq, irq_hw_number_t hwirq) > > > > > +{ > > > > > + struct mvebu_pcie_port *port =3D h->host_data; > > > > > + > > > > > + irq_set_status_flags(virq, IRQ_LEVEL); > > > > > + irq_set_chip_and_handler(virq, &port->intx_irq_chip, handle_lev= el_irq); > > > > > + irq_set_chip_data(virq, port); > > > > > + > > > > > + return 0; > > > > > +} > > > > > + > > > > > +static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_op= s =3D { > > > > > + .map =3D mvebu_pcie_intx_irq_map, > > > > > + .xlate =3D irq_domain_xlate_onecell, > > > > > +}; > > > > > + > > > > > +static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *po= rt) > > > > > +{ > > > > > + struct device *dev =3D &port->pcie->pdev->dev; > > > > > + struct device_node *pcie_intc_node; > > > > > + > > > > > + raw_spin_lock_init(&port->irq_lock); > > > > > + > > > > > + port->intx_irq_chip.name =3D devm_kasprintf(dev, GFP_KERNEL, > > > > > + "mvebu-%s-INTx", > > > > > + port->name); > > > >=20 > > > > That's exactly what I really don't want to see. It prevents sharing= of > > > > the irq_chip structure, and gets in the way of making it const in t= he > > > > future. Yes, I know that some drivers do that. I can't fix those, > > > > because /proc/interrupts is ABI. But I really don't want to see more > > > > of these. > > >=20 > > > Well, I do not understand why it should be shared and with who. HW ha= s N > > > independent IRQ chips for legacy interrupts. And each one will be > > > specified in DT per HW layout / design. > >=20 > > If you have multiple ports, all the ports can share the irq_chip > > structure. Actually scratch that. They *MUST* share the structure. The > > only reason you're not sharing it is to be able to print this useless > > string in /proc/interrupts. >=20 > What is the point of sharing one irq chip if HW has N independent irq > chips (for legacy interrupts)? I do not catch it yet. And I do not care > here for /proc/interrupts, so also I have not caught what do you mean be > last sentence with "the only reason". >=20 > And I still do not see how it could even work to have just one irq chip > and one irq domain as each irq domain needs to know to which port it > belongs, so it can mask/unmask interrupts from correct port. Also > initialization of domain is taking DT node and for each port it is > different. >=20 > So I'm somehow confused here... >=20 > The improvement in this patch is to be able to mask INTA interrupts on > port 1 and let INTA interrupts unmasked on port 2 if there drivers are > interested only for interrupts from device connected to port 2. >=20 > And if all interrupts are going to be shared (again) then it does not > solve any problem. You are completely missing my point. I'm talking about data structures, you're talking about interrupts. You have this: struct mvebu_pcie_port { // Tons of stuff struct irq_chip intx_chip; }; What I want you to do is: struct mvebu_pcie_port { // Tons of stuff }; static struct irq_chip intx_chip =3D { .name =3D "INTx", .irq_mask =3D mvebu_pcie_intx_irq_mask, .irq_unmask =3D mvebu_pcie_intx_irq_unmask; }; That's it. No more, no less. M. --=20 Without deviation from the norm, progress is not possible. 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<877dbcvngf.wl-maz@kernel.org> From: Marc Zyngier To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Marek =?UTF-8?B?QmVow7pu?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts In-Reply-To: <20220106162047.vqykmygs75eimfgy@pali> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> <878rvsvoyo.wl-maz@kernel.org> <20220106162047.vqykmygs75eimfgy@pali> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 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