From: "Alex Bennée" <alex.bennee@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: Eduardo Habkost <eduardo@habkost.net>,
Ben Widawsky <ben.widawsky@intel.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
shameerali.kolothum.thodi@huawei.com, linuxarm@huawei.com,
Igor Mammedov <imammedo@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: RFC: x86 memory map, where to put CXL ranges?
Date: Thu, 09 Dec 2021 14:19:59 +0000 [thread overview]
Message-ID: <877dcdlurx.fsf@linaro.org> (raw)
In-Reply-To: <20211203175734.00002212@Huawei.com>
Jonathan Cameron <Jonathan.Cameron@Huawei.com> writes:
> Hi All,
>
> For CXL emulation we require a couple of types of memory range that
> are then provided to the OS via the CEDT ACPI table.
>
> 1) CXL Host Bridge Structures point to CXL Host Bridge Component Registers.
> Small regions for each CXL Host bridge that are mapped into the memory space.
> 64k each. In theory we may have a huge number of these but in reality I
> think 16 will do for any reasonable system.
>
> 2) CXL Fixed Memory Window Structures (CFMWS)
> Large PA space ranges (multiple TB) to which various CXL devices can be assigned
> and their address decoders appropriately programmed.
> Each such CFMWS will have particular characteristics such as interleaving across
> multiple host bridges. The can potentially be huge but are a system
> characteristic. For emulation purposes it won't matter if they move around
> dependent on what else is the machine has configured. So I'd like to
> just configure their size rather than fully specify them at the command line
> and possibly clash on PA space with something else. Alternatively could
> leave them as fully specified at the command line (address and size) and just
> error out if the hit memory already in use for something else.
>
> Now unfortunately there are no systems out there yet that we can just
> copy the memory map from...
>
> Coming form an Arm background I have only a vague idea of how this should be
> done for x86 so apologies if it is a stupid question.
>
> My current approach is to put these above device_memory and moving
> the pci hole up appropriately.
Which board model would be be talking about here? virt? Or maybe we need
a new one?
If it's virt I would look at extended_memmap which floats above the
configured RAM size and means less shuffling around of the relatively
crowded lower address space.
I have no idea about how this is handled on x86 though.
> Is that the right choice?
>
> On Arm I currently have the Host Bridge Structures low down in the MemMap and the CFMWS
> can go above the device memory. Comments on that also welcome.
>
> In Ben's RFC the host bridge component register location was marked as a TODO
> and a arbitrary address used in the meantime so time to figure out how to clean
> that up.
>
> Thanks,
>
> Jonathan
--
Alex Bennée
next prev parent reply other threads:[~2021-12-09 14:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 17:57 RFC: x86 memory map, where to put CXL ranges? Jonathan Cameron via
2021-12-09 14:19 ` Alex Bennée [this message]
2021-12-09 15:47 ` Jonathan Cameron via
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