Re: [RFC PATCH 3/3] target/avr: Fix SBRC/SBRS instructions

["Alex Bennée" <alex.bennee@linaro.org>]

Philippe Mathieu-Daudé <f4bug@amsat.org> writes:

> SBRC/SBRS instructions seem to be inverted.

I'm having trouble following exactly how the skip logic is meant to
work. Intuitively I would expect a skip if clear to be TCG_COND_EQ
because that is true if bit & mask is compared to 0 but it's not clear
that what happens.

It would be easier if we actually had some instruction tests. I see
gcc-avr is a thing.

>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/avr/translate.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index fe03e676df..2f77fe3ba7 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -1385,7 +1385,7 @@ static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
>  {
>      TCGv Rr = cpu_r[a->rr];
>  
> -    ctx->skip_cond = TCG_COND_EQ;
> +    ctx->skip_cond = TCG_COND_NE;
>      ctx->skip_var0 = tcg_temp_new();
>      ctx->free_skip_var0 = true;
>  
> @@ -1401,7 +1401,7 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
>  {
>      TCGv Rr = cpu_r[a->rr];
>  
> -    ctx->skip_cond = TCG_COND_NE;
> +    ctx->skip_cond = TCG_COND_EQ;
>      ctx->skip_var0 = tcg_temp_new();
>      ctx->free_skip_var0 = true;


-- 
Alex Bennée