From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, aurelien@aurel32.net, amarkovic@wavecomp.com
Subject: Re: [Qemu-devel] [PATCH 1/2] target/mips: Improve performance for MSA binary operations
Date: Sun, 02 Jun 2019 14:22:14 +0100 [thread overview]
Message-ID: <877ea4dsvt.fsf@zen.linaroharston> (raw)
In-Reply-To: <1551718283-4487-2-git-send-email-mateja.marjanovic@rt-rk.com>
Mateja Marjanovic <mateja.marjanovic@rt-rk.com> writes:
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> Eliminate loops for better performance.
Have you done any measurements of the bellow loop unrolling? Because
this is something that maybe we can achieve and let the compiler make
the choice.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> ---
> target/mips/msa_helper.c | 43 ++++++++++++++++++++++++++++++-------------
> 1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index 4c7ec05..1152fda 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -804,28 +804,45 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
> wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
> wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
> wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
> \
If we can ensure alignment for the various vector registers then the
compiler always has the option of using host vectors (certainly for int
and logic operations).
> - uint32_t i; \
> \
> switch (df) { \
> case DF_BYTE: \
> - for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
> - pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
> - } \
> + pwd->b[0] = msa_ ## func ## _df(df, pws->b[0], pwt->b[0]); \
> + pwd->b[1] = msa_ ## func ## _df(df, pws->b[1], pwt->b[1]); \
> + pwd->b[2] = msa_ ## func ## _df(df, pws->b[2], pwt->b[2]); \
> + pwd->b[3] = msa_ ## func ## _df(df, pws->b[3], pwt->b[3]); \
> + pwd->b[4] = msa_ ## func ## _df(df, pws->b[4], pwt->b[4]); \
> + pwd->b[5] = msa_ ## func ## _df(df, pws->b[5], pwt->b[5]); \
> + pwd->b[6] = msa_ ## func ## _df(df, pws->b[6], pwt->b[6]); \
> + pwd->b[7] = msa_ ## func ## _df(df, pws->b[7], pwt->b[7]); \
> + pwd->b[8] = msa_ ## func ## _df(df, pws->b[8], pwt->b[8]); \
> + pwd->b[9] = msa_ ## func ## _df(df, pws->b[9], pwt->b[9]); \
> + pwd->b[10] = msa_ ## func ## _df(df, pws->b[10], pwt->b[10]); \
> + pwd->b[11] = msa_ ## func ## _df(df, pws->b[11], pwt->b[11]); \
> + pwd->b[12] = msa_ ## func ## _df(df, pws->b[12], pwt->b[12]); \
> + pwd->b[13] = msa_ ## func ## _df(df, pws->b[13], pwt->b[13]); \
> + pwd->b[14] = msa_ ## func ## _df(df, pws->b[14], pwt->b[14]); \
> + pwd->b[15] = msa_ ## func ## _df(df, pws->b[15], pwt->b[15]); \
> break; \
> case DF_HALF: \
> - for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
> - pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
> - } \
> + pwd->h[0] = msa_ ## func ## _df(df, pws->h[0], pwt->h[0]); \
> + pwd->h[1] = msa_ ## func ## _df(df, pws->h[1], pwt->h[1]); \
> + pwd->h[2] = msa_ ## func ## _df(df, pws->h[2], pwt->h[2]); \
> + pwd->h[3] = msa_ ## func ## _df(df, pws->h[3], pwt->h[3]); \
> + pwd->h[4] = msa_ ## func ## _df(df, pws->h[4], pwt->h[4]); \
> + pwd->h[5] = msa_ ## func ## _df(df, pws->h[5], pwt->h[5]); \
> + pwd->h[6] = msa_ ## func ## _df(df, pws->h[6], pwt->h[6]); \
> + pwd->h[7] = msa_ ## func ## _df(df, pws->h[7], pwt->h[7]); \
> break; \
> case DF_WORD: \
> - for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
> - pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
> - } \
> + pwd->w[0] = msa_ ## func ## _df(df, pws->w[0], pwt->w[0]); \
> + pwd->w[1] = msa_ ## func ## _df(df, pws->w[1], pwt->w[1]); \
> + pwd->w[2] = msa_ ## func ## _df(df, pws->w[2], pwt->w[2]); \
> + pwd->w[3] = msa_ ## func ## _df(df, pws->w[3], pwt->w[3]); \
> break; \
> case DF_DOUBLE: \
> - for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
> - pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
> - } \
> + pwd->d[0] = msa_ ## func ## _df(df, pws->d[0], pwt->d[0]); \
> + pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \
> break; \
> default: \
> assert(0); \
--
Alex Bennée
next prev parent reply other threads:[~2019-06-02 13:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-04 16:51 [Qemu-devel] [PATCH 0/2] target/mips: Improve performance for MSA binary operations Mateja Marjanovic
2019-03-04 16:51 ` [Qemu-devel] [PATCH 1/2] " Mateja Marjanovic
2019-06-01 14:16 ` Aleksandar Markovic
2019-06-02 7:06 ` Aleksandar Markovic
2019-06-03 9:46 ` Mateja Marjanovic
2019-06-02 13:22 ` Alex Bennée [this message]
2019-06-03 13:10 ` Aleksandar Markovic
2019-06-03 13:29 ` Mateja Marjanovic
2019-03-04 16:51 ` [Qemu-devel] [PATCH 2/2] target/mips: Tests for binary integer MSA instruction (add, adds, hadd...) Mateja Marjanovic
2019-03-04 18:43 ` Aleksandar Markovic
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