From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b87sm4010334wmi.0.2017.01.27.05.43.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 05:43:05 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTPS id 46C753E008E; Fri, 27 Jan 2017 13:43:05 +0000 (GMT) References: <1485285380-10565-1-git-send-email-peter.maydell@linaro.org> <1485285380-10565-5-git-send-email-peter.maydell@linaro.org> User-agent: mu4e 0.9.19; emacs 25.1.91.4 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Liviu Ionescu Subject: Re: [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR In-reply-to: <1485285380-10565-5-git-send-email-peter.maydell@linaro.org> Date: Fri, 27 Jan 2017 13:43:05 +0000 Message-ID: <877f5gaaae.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-TUID: 2jqo9u4KKVyB Peter Maydell writes: > From: Michael Davidsaver > > Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and > MMFAR. For the moment these simply read as written (with some basic > handling of RAZ/WI bits and W1C semantics). > > Signed-off-by: Michael Davidsaver > [PMM: drop warning about setting unimplemented CCR bits; > tweak commit message; add DFSR] > Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée > --- > hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++---------- > 1 file changed, 32 insertions(+), 10 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 81dcb83..60e72d7 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -228,8 +228,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) > /* TODO: Implement SLEEPONEXIT. */ > return 0; > case 0xd14: /* Configuration Control. */ > - /* TODO: Implement Configuration Control bits. */ > - return 0; > + return cpu->env.v7m.ccr; > case 0xd24: /* System Handler Status. */ > val = 0; > if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); > @@ -248,16 +247,19 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) > if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18); > return val; > case 0xd28: /* Configurable Fault Status. */ > - /* TODO: Implement Fault Status. */ > - qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n"); > - return 0; > + return cpu->env.v7m.cfsr; > case 0xd2c: /* Hard Fault Status. */ > + return cpu->env.v7m.hfsr; > case 0xd30: /* Debug Fault Status. */ > - case 0xd34: /* Mem Manage Address. */ > + return cpu->env.v7m.dfsr; > + case 0xd34: /* MMFAR MemManage Fault Address */ > + return cpu->env.v7m.mmfar; > case 0xd38: /* Bus Fault Address. */ > + return cpu->env.v7m.bfar; > case 0xd3c: /* Aux Fault Status. */ > /* TODO: Implement fault status registers. */ > - qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n"); > + qemu_log_mask(LOG_UNIMP, > + "Aux Fault status registers unimplemented\n"); > return 0; > case 0xd40: /* PFR0. */ > return 0x00000030; > @@ -366,9 +368,19 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) > } > break; > case 0xd10: /* System Control. */ > - case 0xd14: /* Configuration Control. */ > /* TODO: Implement control registers. */ > - qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n"); > + qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); > + break; > + case 0xd14: /* Configuration Control. */ > + /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ > + value &= (R_V7M_CCR_STKALIGN_MASK | > + R_V7M_CCR_BFHFNMIGN_MASK | > + R_V7M_CCR_DIV_0_TRP_MASK | > + R_V7M_CCR_UNALIGN_TRP_MASK | > + R_V7M_CCR_USERSETMPEND_MASK | > + R_V7M_CCR_NONBASETHRDENA_MASK); > + > + cpu->env.v7m.ccr = value; > break; > case 0xd24: /* System Handler Control. */ > /* TODO: Real hardware allows you to set/clear the active bits > @@ -378,13 +390,23 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) > s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; > break; > case 0xd28: /* Configurable Fault Status. */ > + cpu->env.v7m.cfsr &= ~value; /* W1C */ > + break; > case 0xd2c: /* Hard Fault Status. */ > + cpu->env.v7m.hfsr &= ~value; /* W1C */ > + break; > case 0xd30: /* Debug Fault Status. */ > + cpu->env.v7m.dfsr &= ~value; /* W1C */ > + break; > case 0xd34: /* Mem Manage Address. */ > + cpu->env.v7m.mmfar = value; > + return; > case 0xd38: /* Bus Fault Address. */ > + cpu->env.v7m.bfar = value; > + return; > case 0xd3c: /* Aux Fault Status. */ > qemu_log_mask(LOG_UNIMP, > - "NVIC: fault status registers unimplemented\n"); > + "NVIC: Aux fault status registers unimplemented\n"); > break; > case 0xf00: /* Software Triggered Interrupt Register */ > if ((value & 0x1ff) < s->num_irq) { -- Alex Bennée From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX6o5-0002yh-F4 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:43:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX6o2-0002om-69 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:43:13 -0500 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]:35121) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX6o1-0002o7-SY for qemu-devel@nongnu.org; Fri, 27 Jan 2017 08:43:10 -0500 Received: by mail-wm0-x232.google.com with SMTP id r126so117674394wmr.0 for ; Fri, 27 Jan 2017 05:43:08 -0800 (PST) References: <1485285380-10565-1-git-send-email-peter.maydell@linaro.org> <1485285380-10565-5-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1485285380-10565-5-git-send-email-peter.maydell@linaro.org> Date: Fri, 27 Jan 2017 13:43:05 +0000 Message-ID: <877f5gaaae.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Liviu Ionescu Peter Maydell writes: > From: Michael Davidsaver > > Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and > MMFAR. For the moment these simply read as written (with some basic > handling of RAZ/WI bits and W1C semantics). > > Signed-off-by: Michael Davidsaver > [PMM: drop warning about setting unimplemented CCR bits; > tweak commit message; add DFSR] > Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée > --- > hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++---------- > 1 file changed, 32 insertions(+), 10 deletions(-) > > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index 81dcb83..60e72d7 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -228,8 +228,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) > /* TODO: Implement SLEEPONEXIT. */ > return 0; > case 0xd14: /* Configuration Control. */ > - /* TODO: Implement Configuration Control bits. */ > - return 0; > + return cpu->env.v7m.ccr; > case 0xd24: /* System Handler Status. */ > val = 0; > if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); > @@ -248,16 +247,19 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) > if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18); > return val; > case 0xd28: /* Configurable Fault Status. */ > - /* TODO: Implement Fault Status. */ > - qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n"); > - return 0; > + return cpu->env.v7m.cfsr; > case 0xd2c: /* Hard Fault Status. */ > + return cpu->env.v7m.hfsr; > case 0xd30: /* Debug Fault Status. */ > - case 0xd34: /* Mem Manage Address. */ > + return cpu->env.v7m.dfsr; > + case 0xd34: /* MMFAR MemManage Fault Address */ > + return cpu->env.v7m.mmfar; > case 0xd38: /* Bus Fault Address. */ > + return cpu->env.v7m.bfar; > case 0xd3c: /* Aux Fault Status. */ > /* TODO: Implement fault status registers. */ > - qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n"); > + qemu_log_mask(LOG_UNIMP, > + "Aux Fault status registers unimplemented\n"); > return 0; > case 0xd40: /* PFR0. */ > return 0x00000030; > @@ -366,9 +368,19 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) > } > break; > case 0xd10: /* System Control. */ > - case 0xd14: /* Configuration Control. */ > /* TODO: Implement control registers. */ > - qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n"); > + qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); > + break; > + case 0xd14: /* Configuration Control. */ > + /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ > + value &= (R_V7M_CCR_STKALIGN_MASK | > + R_V7M_CCR_BFHFNMIGN_MASK | > + R_V7M_CCR_DIV_0_TRP_MASK | > + R_V7M_CCR_UNALIGN_TRP_MASK | > + R_V7M_CCR_USERSETMPEND_MASK | > + R_V7M_CCR_NONBASETHRDENA_MASK); > + > + cpu->env.v7m.ccr = value; > break; > case 0xd24: /* System Handler Control. */ > /* TODO: Real hardware allows you to set/clear the active bits > @@ -378,13 +390,23 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) > s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; > break; > case 0xd28: /* Configurable Fault Status. */ > + cpu->env.v7m.cfsr &= ~value; /* W1C */ > + break; > case 0xd2c: /* Hard Fault Status. */ > + cpu->env.v7m.hfsr &= ~value; /* W1C */ > + break; > case 0xd30: /* Debug Fault Status. */ > + cpu->env.v7m.dfsr &= ~value; /* W1C */ > + break; > case 0xd34: /* Mem Manage Address. */ > + cpu->env.v7m.mmfar = value; > + return; > case 0xd38: /* Bus Fault Address. */ > + cpu->env.v7m.bfar = value; > + return; > case 0xd3c: /* Aux Fault Status. */ > qemu_log_mask(LOG_UNIMP, > - "NVIC: fault status registers unimplemented\n"); > + "NVIC: Aux fault status registers unimplemented\n"); > break; > case 0xf00: /* Software Triggered Interrupt Register */ > if ((value & 0x1ff) < s->num_irq) { -- Alex Bennée