From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Date: Tue, 01 Nov 2016 21:28:06 +0200 Message-ID: <877f8nj8zd.fsf@intel.com> References: <1478026080-2925-1-git-send-email-dhinakaran.pandiyan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 68D706E0D8 for ; Tue, 1 Nov 2016 19:28:14 +0000 (UTC) In-Reply-To: <1478026080-2925-1-git-send-email-dhinakaran.pandiyan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Dhinakaran Pandiyan List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCAwMSBOb3YgMjAxNiwgRGhpbmFrYXJhbiBQYW5kaXlhbiA8ZGhpbmFrYXJhbi5wYW5k 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SmFuaSBOaWt1bGEsIEludGVsIE9wZW4gU291cmNlIFRlY2hub2xvZ3kgQ2VudGVyCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVk ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com ([192.55.52.43]:9267 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750749AbcKAT2O (ORCPT ); Tue, 1 Nov 2016 15:28:14 -0400 From: Jani Nikula To: Dhinakaran Pandiyan , intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, libin.yang@intel.com, Dhinakaran Pandiyan , stable@vger.kernel.org Subject: Re: [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio In-Reply-To: <1478026080-2925-1-git-send-email-dhinakaran.pandiyan@intel.com> References: <1478026080-2925-1-git-send-email-dhinakaran.pandiyan@intel.com> Date: Tue, 01 Nov 2016 21:28:06 +0200 Message-ID: <877f8nj8zd.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Tue, 01 Nov 2016, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays > cycling on/off. > > From BSpec: > "Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)] > Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio > enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may > be audio corruption or screen corruption." > > Since, some DP configurations (e.g., MST) use port width x4 and HBR2 > link rate, let's increase the cdclk to >= 432 MHz to enable audio for those > cases. > > v4: Changed commit message > v3: Combine BDW pixel rate adjustments into a function (Jani) > v2: Restrict fix to BDW > Retain the set cdclk across modesets (Ville) > Cc: stable@vger.kernel.org > Signed-off-by: Dhinakaran Pandiyan > Reviewed-by: Ville Syrjälä > Reviewed-by: Jani Nikula Yup. > --- > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 895b3dc..37483ee 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10261,6 +10261,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > bxt_set_cdclk(to_i915(dev), req_cdclk); > } > > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > + int pixel_rate) > +{ > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > + if (crtc_state->ips_enabled) > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + > + /* BSpec says "Do not use DisplayPort with CDCLK less than > + * 432 MHz, audio enabled, port width x4, and link rate > + * HBR2 (5.4 GHz), or else there may be audio corruption or > + * screen corruption." > + */ > + if (intel_crtc_has_dp_encoder(crtc_state) && > + crtc_state->has_audio && > + crtc_state->port_clock >= 540000 && > + crtc_state->lane_count == 4) > + pixel_rate = max(432000, pixel_rate); > + > + return pixel_rate; > +} > + > /* compute the max rate for new configuration */ > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > { > @@ -10286,9 +10307,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + if (IS_BROADWELL(dev_priv)) > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > + pixel_rate); > > intel_state->min_pixclk[i] = pixel_rate; > } -- Jani Nikula, Intel Open Source Technology Center