From: Jani Nikula <jani.nikula@linux.intel.com>
To: Gaurav K Singh <gaurav.k.singh@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Subject: Re: [PATCH 6/9] drm/i915: Dsipll clk to be enabled for DSI1 in case of dual link configuration
Date: Wed, 24 Sep 2014 12:34:59 +0300 [thread overview]
Message-ID: <877g0tmke4.fsf@intel.com> (raw)
In-Reply-To: <1411548418-26525-7-git-send-email-gaurav.k.singh@intel.com>
On Wed, 24 Sep 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..2464089 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>
> dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>
> + if (intel_dsi->dual_link)
> + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
> DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
> dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>
> @@ -271,12 +274,11 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>
> mutex_unlock(&dev_priv->dpio_lock);
>
> - if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
> - DRM_ERROR("DSI PLL lock failed\n");
> - return;
> - }
> -
> - DRM_DEBUG_KMS("DSI PLL locked\n");
> + tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
Is there no need to wait for some timeout for the pll to lock?
> + if (tmp & DSI_PLL_LOCK)
> + DRM_DEBUG_KMS("DSI PLL locked\n");
> + else
> + DRM_DEBUG_KMS("DSI PLL lock failed\n");
Please keep the happy day scenario without indent, and bail out on the
fail paths.
> }
>
> void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-09-24 9:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-24 8:46 [PATCH 0/9] BYT DSI Dual Link Support Gaurav K Singh
2014-09-24 8:46 ` [PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
2014-09-24 8:46 ` [PATCH 2/9] drm/i915: MIPI Sequence to be sent to the DSI Controller based on the port no from VBT Gaurav K Singh
2014-09-24 8:46 ` [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration Gaurav K Singh
2014-09-24 9:27 ` Jani Nikula
2014-10-21 6:30 ` Singh, Gaurav K
2014-10-21 12:12 ` Daniel Vetter
2014-10-21 13:19 ` Jani Nikula
2014-09-24 8:46 ` [PATCH 4/9] drm/i915: Pixel Clock and pixel overlap related changes for dual link Configuration Gaurav K Singh
2014-09-24 9:23 ` Jani Nikula
2014-09-24 8:46 ` [PATCH 5/9] drm/i915: SHUTDOWN & Turn ON packets to be sent for both MIPI Ports in case of " Gaurav K Singh
2014-09-24 9:32 ` Jani Nikula
2014-09-25 12:54 ` Shobhit Kumar
2014-09-25 13:39 ` Jani Nikula
2014-09-25 14:22 ` Shobhit Kumar
2014-09-24 8:46 ` [PATCH 6/9] drm/i915: Dsipll clk to be enabled for DSI1 in case of dual link configuration Gaurav K Singh
2014-09-24 9:34 ` Jani Nikula [this message]
2014-09-24 8:46 ` [PATCH 7/9] drm/i915: MIPI Timings related changes for dual link Configuration Gaurav K Singh
2014-09-24 8:46 ` [PATCH 8/9] drm/i915: MIPI encoder disable " Gaurav K Singh
2014-09-24 8:46 ` [PATCH 9/9] drm/i915: MIPI Encoder enable related changes for dual link configuration Gaurav K Singh
2014-09-24 9:01 ` [PATCH 0/9] BYT DSI Dual Link Support Daniel Vetter
2014-09-25 12:47 ` Shobhit Kumar
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