Re: [PATCH 49/62] drm/i915/bdw: Use The GT mailbox for IPS enable/disable

[Jani Nikula <jani.nikula@linux.intel.com>]

On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
>
> CC: Art Runyan <arthur.j.runyan@intel.com>
> Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

The WARN_ON()s may be a bit loud, but

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++----------
>  3 files changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a2e967..f222eb4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1803,7 +1803,7 @@ struct drm_i915_file_private {
>  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
>  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>  
> -#define HAS_IPS(dev)		(IS_ULT(dev))
> +#define HAS_IPS(dev)		(IS_ULT(dev) || IS_BROADWELL(dev))
>  
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_GEN8(dev))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a65f92..65f9631 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4932,6 +4932,7 @@
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   DISPLAY_IPS_CONTROL			0x19
>  #define GEN6_PCODE_DATA				0x138128
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fce3b0d..fc4b4cf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3347,15 +3347,26 @@ void hsw_enable_ips(struct intel_crtc *crtc)
>  	 * only after intel_enable_plane. And intel_enable_plane already waits
>  	 * for a vblank, so all we need to do here is to enable the IPS bit. */
>  	assert_plane_enabled(dev_priv, crtc->plane);
> -	I915_WRITE(IPS_CTL, IPS_ENABLE);
> -
> -	/* The bit only becomes 1 in the next vblank, so this wait here is
> -	 * essentially intel_wait_for_vblank. If we don't have this and don't
> -	 * wait for vblanks until the end of crtc_enable, then the HW state
> -	 * readout code will complain that the expected IPS_CTL value is not the
> -	 * one we read. */
> -	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
> -		DRM_ERROR("Timed out waiting for IPS enable\n");
> +	if (IS_BROADWELL(crtc->base.dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +		/* Quoting Art Runyan: "its not safe to expect any particular
> +		 * value in IPS_CTL bit 31 after enabling IPS through the
> +		 * mailbox." Therefore we need to defer waiting on the state
> +		 * change.
> +		 * TODO: need to fix this for state checker
> +		 */
> +	} else {
> +		I915_WRITE(IPS_CTL, IPS_ENABLE);
> +		/* The bit only becomes 1 in the next vblank, so this wait here
> +		 * is essentially intel_wait_for_vblank. If we don't have this
> +		 * and don't wait for vblanks until the end of crtc_enable, then
> +		 * the HW state readout code will complain that the expected
> +		 * IPS_CTL value is not the one we read. */
> +		if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
> +			DRM_ERROR("Timed out waiting for IPS enable\n");
> +	}
>  }
>  
>  void hsw_disable_ips(struct intel_crtc *crtc)
> @@ -3367,7 +3378,12 @@ void hsw_disable_ips(struct intel_crtc *crtc)
>  		return;
>  
>  	assert_plane_enabled(dev_priv, crtc->plane);
> -	I915_WRITE(IPS_CTL, 0);
> +	if (IS_BROADWELL(crtc->base.dev)) {
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else
> +		I915_WRITE(IPS_CTL, 0);
>  	POSTING_READ(IPS_CTL);
>  
>  	/* We need to wait for a vblank before we can disable the plane. */
> -- 
> 1.8.4.2
>
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-- 
Jani Nikula, Intel Open Source Technology Center