From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40653) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzKKi-0005Tz-VZ for qemu-devel@nongnu.org; Sun, 19 Feb 2012 22:54:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RzKKX-00087R-28 for qemu-devel@nongnu.org; Sun, 19 Feb 2012 22:54:36 -0500 Received: from ozlabs.org ([203.10.76.45]:58311) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzKKW-00087B-OH for qemu-devel@nongnu.org; Sun, 19 Feb 2012 22:54:25 -0500 From: Rusty Russell In-Reply-To: References: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> <1326487969-12462-3-git-send-email-peter.maydell@linaro.org> <87fwf5ebjw.fsf@rustcorp.com.au> <87vcnyc7cg.fsf@rustcorp.com.au> <87fwe68lt0.fsf@rustcorp.com.au> Date: Mon, 20 Feb 2012 14:22:00 +1030 Message-ID: <877gzi88m7.fsf@rustcorp.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Android-virt] [PATCH] arm: make sure that number of irqs can be represented in GICD_TYPER. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christoffer Dall Cc: Peter Maydell , qemu-devel@nongnu.org, android-virt@lists.cs.columbia.edu, patches@linaro.org On Sun, 19 Feb 2012 18:40:08 -0500, Christoffer Dall wrote: > On Sun, Feb 19, 2012 at 6:07 PM, Rusty Russell wr= ote: > > We currently assume that the number of interrupts (ITLinesNumber in > > the architecture reference manual) is divisible by 32, since we > > present it to the guest when it reads GICD_TYPER (in gic_dist_readb()) > > as (N - 32) / 1. > > > > Signed-off-by: Rusty Russell > > > > diff --git a/hw/arm_gic.c b/hw/arm_gic.c > > index fa6a60a..6446800 100644 > > --- a/hw/arm_gic.c > > +++ b/hw/arm_gic.c > > @@ -818,6 +818,15 @@ static void gic_init(gic_state *s, int num_irq) > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 hw_error("requested %u interrupt lines exce= eds GIC maximum %d\n", > > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0num_irq, = GIC_MAXIRQ); > > =C2=A0 =C2=A0 } > > + =C2=A0 =C2=A0/* ITLinesNumber is represented as (N - 32) / 1 (see > > + =C2=A0 =C2=A0 * gic_dist_readb) so this is an implementation imposed > > + =C2=A0 =C2=A0 * restriction, not an architectural one: > > + =C2=A0 =C2=A0 */ >=20 > What is this division by 1? Isn't (N - 32) / 1 =3D=3D (N - 32) and how > does that explain the division. Was it (N / 32) - 1? Or is this a > cast? Or am I missing something completely? That's hilarious; we were concentrating so hard on the wording of the comment, we didn't notice that I completely screwed the content :) It is, of course, (N / 32) - 1: static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) { ... if (offset =3D=3D 4) return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5); I'll fix it, thanks! Rusty.