From: Andi Kleen <andi@firstfloor.org>
To: Shaohua Li <shaohua.li@intel.com>
Cc: lkml <linux-kernel@vger.kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Ingo Molnar <mingo@elte.hu>,
"Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>
Subject: Re: [patch]pageattr: cache flush before tlb flush
Date: Tue, 19 Aug 2008 08:38:28 +0200 [thread overview]
Message-ID: <877iad1pcr.fsf@basil.nowhere.org> (raw)
In-Reply-To: <1219026451.16428.4.camel@sli10-desk.sh.intel.com> (Shaohua Li's message of "Mon, 18 Aug 2008 10:27:31 +0800")
Shaohua Li <shaohua.li@intel.com> writes:
> clflush uses a virtual address but cache line is physical indexed in
> x86. In my understanding, clflush will do some pagetable walk, so doing
> cache flush first should reduce some pagetable walk.
The SDM describes the exact sequence how this should be done.
Linux unfortunately skips one step currently, but it's not a good
idea to diverge even more.
-Andi
prev parent reply other threads:[~2008-08-19 6:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-08-18 2:27 [patch]pageattr: cache flush before tlb flush Shaohua Li
2008-08-19 5:09 ` H. Peter Anvin
2008-08-19 5:24 ` Li, Shaohua
2008-08-19 6:38 ` Andi Kleen [this message]
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