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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1724118999; h=Message-ID:Date:MIME-Version:Subject:To:From:Content-Type; bh=nA809LtVfKWVOwke62uMihCDUdWhyXWDWY+4FRYQ9ag=; b=kq1fI1ykY0zgzVhsFh5sIWX/fUiHxq0T8T8lsjKjkixognPZpCfP8gxAkvyrY7+Pr+pEFR45j04JC5wsFRyQUYPfBlKgmk0MFgouxxr5TL4QoVliJ9wmX6lhGIv+v4gQB69rbUQRRSQxgz19D+afJDFsihA5ftmQAGK8juGsYzY= Received: from 30.166.65.10(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0WDGbxRD_1724118996) by smtp.aliyun-inc.com; Tue, 20 Aug 2024 09:56:37 +0800 Message-ID: <8788fae2-14ca-4af2-a075-bf20a533f540@linux.alibaba.com> Date: Tue, 20 Aug 2024 09:56:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> <20240813113436.831-9-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: LIU Zhiwei In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.118; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-118.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2024/8/14 17:13, Richard Henderson wrote: > On 8/13/24 21:34, LIU Zhiwei wrote: >> From: TANG Tiancheng >> >> Signed-off-by: TANG Tiancheng >> Reviewed-by: Liu Zhiwei >> --- >>   tcg/riscv/tcg-target-con-set.h |  1 + >>   tcg/riscv/tcg-target.c.inc     | 33 +++++++++++++++++++++++++++++++++ >>   2 files changed, 34 insertions(+) >> >> diff --git a/tcg/riscv/tcg-target-con-set.h >> b/tcg/riscv/tcg-target-con-set.h >> index d73a62b0f2..8a0de18257 100644 >> --- a/tcg/riscv/tcg-target-con-set.h >> +++ b/tcg/riscv/tcg-target-con-set.h >> @@ -23,3 +23,4 @@ C_O1_I4(r, r, rI, rM, rM) >>   C_O2_I4(r, r, rZ, rZ, rM, rM) >>   C_O0_I2(v, r) >>   C_O1_I1(v, r) >> +C_O1_I2(v, v, v) >> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc >> index f60913e805..650b5eff1a 100644 >> --- a/tcg/riscv/tcg-target.c.inc >> +++ b/tcg/riscv/tcg-target.c.inc >> @@ -289,6 +289,12 @@ typedef enum { >>       OPC_VSE32_V = 0x6027 | V_SUMOP, >>       OPC_VSE64_V = 0x7027 | V_SUMOP, >>   +    OPC_VADD_VV = 0x57 | V_OPIVV, >> +    OPC_VSUB_VV = 0x8000057 | V_OPIVV, >> +    OPC_VAND_VV = 0x24000057 | V_OPIVV, >> +    OPC_VOR_VV = 0x28000057 | V_OPIVV, >> +    OPC_VXOR_VV = 0x2c000057 | V_OPIVV, >> + >>       OPC_VMV_V_V = 0x5e000057 | V_OPIVV, >>       OPC_VMV_V_I = 0x5e000057 | V_OPIVI, >>       OPC_VMV_V_X = 0x5e000057 | V_OPIVX, >> @@ -2158,6 +2164,21 @@ static void tcg_out_vec_op(TCGContext *s, >> TCGOpcode opc, >>       case INDEX_op_st_vec: >>           tcg_out_st(s, type, a0, a1, a2); >>           break; >> +    case INDEX_op_add_vec: >> +        tcg_out_opc_vv(s, OPC_VADD_VV, a0, a1, a2, true); >> +        break; >> +    case INDEX_op_sub_vec: >> +        tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2, true); >> +        break; >> +    case INDEX_op_and_vec: >> +        tcg_out_opc_vv(s, OPC_VAND_VV, a0, a1, a2, true); >> +        break; >> +    case INDEX_op_or_vec: >> +        tcg_out_opc_vv(s, OPC_VOR_VV, a0, a1, a2, true); >> +        break; >> +    case INDEX_op_xor_vec: >> +        tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); >> +        break; > > As with load/store/move, and/or/xor can avoid changing element type. > Thus I think the vtype setup before the switch is premature. Agree. We have implemented this feature on the v2 patch set. Thanks, Zhiwei > > > r~