From: Thomas Gleixner <tglx@kernel.org>
To: Maulik Shah <maulik.shah@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-gpio@vger.kernel.org,
Sneh Mankad <sneh.mankad@oss.qualcomm.com>,
Maulik Shah <maulik.shah@oss.qualcomm.com>
Subject: Re: [PATCH v2 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper
Date: Wed, 03 Jun 2026 17:25:31 +0200 [thread overview]
Message-ID: <878q8v7ij8.ffs@fw13> (raw)
In-Reply-To: <20260526-hamoa_pdc-v2-3-f6857af1ce91@oss.qualcomm.com>
On Tue, May 26 2026 at 16:24, Maulik Shah wrote:
> pdc->enable_intr() function already points to respective version
> specific enable function. pdc_enable_intr() now only kept as wrapper.
> Remove the wrapper and invoke pdc->enable_intr() from caller.
>
> Locking in pdc_enable_intr() applies lock to all pdc->enable_intr()
> however its only required for pdc_enable_intr_bank() which uses
> a shared bank across all interrupts. pdc_enable_intr_cfg() do not
> required locking as IRQ_CFG registers are one per interrupt. Move
> locking accordingly.
>
> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
> ---
> drivers/irqchip/qcom-pdc.c | 18 +++++++-----------
> 1 file changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
> index 8f7802139e4e..db76737646e1 100644
> --- a/drivers/irqchip/qcom-pdc.c
> +++ b/drivers/irqchip/qcom-pdc.c
> @@ -201,11 +201,14 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
> static void pdc_enable_intr_bank(int pin_out, bool on)
> {
> unsigned long enable;
> + unsigned long flags;
> u32 index, mask;
>
> index = FIELD_GET(GENMASK(31, 5), pin_out);
> mask = FIELD_GET(GENMASK(4, 0), pin_out);
>
> + raw_spin_lock_irqsave(&pdc->lock, flags);
guard()
next prev parent reply other threads:[~2026-06-03 15:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 10:54 [PATCH v2 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state Maulik Shah
2026-05-26 10:54 ` [PATCH v2 1/8] irqchip/qcom-pdc: restructure version support Maulik Shah
2026-06-03 15:33 ` Thomas Gleixner
2026-05-26 10:54 ` [PATCH v2 2/8] irqchip/qcom-pdc: Move all statics to struct pdc_desc Maulik Shah
2026-06-03 15:24 ` Thomas Gleixner
2026-05-26 10:54 ` [PATCH v2 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper Maulik Shah
2026-05-26 12:34 ` Stephan Gerhold
2026-06-03 15:25 ` Thomas Gleixner [this message]
2026-05-26 10:54 ` [PATCH v2 4/8] irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI Maulik Shah
2026-06-03 15:27 ` Thomas Gleixner
2026-05-26 10:54 ` [PATCH v2 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode Maulik Shah
2026-05-26 12:22 ` Stephan Gerhold
2026-06-03 15:36 ` Thomas Gleixner
2026-05-26 10:54 ` [PATCH v2 6/8] pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller Maulik Shah
2026-05-26 10:54 ` [PATCH v2 7/8] Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" Maulik Shah
2026-05-26 10:54 ` [PATCH v2 8/8] arm64: dts: qcom: x1e80100: Add deepest idle state Maulik Shah
2026-05-26 11:59 ` [PATCH v2 0/8] x1e80100: Enable PDC wake GPIOs and " Stephan Gerhold
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