From: Mattijs Korpershoek <mkorpershoek@kernel.org>
To: Anshul Dalal <anshuld@ti.com>,
Siddharth Vadapalli <s-vadapalli@ti.com>,
trini@konsulko.com, lukma@denx.de, mkorpershoek@kernel.org
Cc: u-boot@lists.denx.de, srk@ti.com
Subject: Re: [PATCH] common: spl: spl_dfu.c: Fix warning associated with PCI subclass_code
Date: Thu, 12 Mar 2026 09:58:03 +0100 [thread overview]
Message-ID: <878qbxmnl0.fsf@kernel.org> (raw)
In-Reply-To: <DGVFQRGRKPW4.3LLLZIHTKSFG2@ti.com>
Hi Anshul,
On Fri, Mar 06, 2026 at 10:34, Anshul Dalal <anshuld@ti.com> wrote:
> On Thu Mar 5, 2026 at 4:08 PM IST, Siddharth Vadapalli wrote:
>> The subclass_code member of the pci_ep_header structure is a 1-byte
>> field. The macro PCI_CLASS_MEMORY_RAM is a concetation of baseclass_code
>> and subclass_code as follows:
>> PCI_BASE_CLASS_MEMORY: 0x05
>> Subclass Code for RAM: 0x00
>> PCI_CLASS_MEMORY_RAM: 0x0500
>> Hence, instead of extracting it via an implicity type conversion from int
>> to u8 which throws a warning, explicitly mask the bits to extract the
>> subclass_code.
>>
>> Fixes: cde77583cf0b ("spl: Add support for Device Firmware Upgrade (DFU) over PCIe")
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>
> I was able to reproduce the issue on am62x_evm_a53_defconfig with the
> following diff:
>
> diff --git a/arch/arm/mach-k3/include/mach/am62_spl.h b/arch/arm/mach-k3/include/mach/am62_spl.h
> index 2c9139d2cc0..07ae5e99e49 100644
> --- a/arch/arm/mach-k3/include/mach/am62_spl.h
> +++ b/arch/arm/mach-k3/include/mach/am62_spl.h
> @@ -12,6 +12,7 @@
> #define BOOT_DEVICE_OSPI 0x01
> #define BOOT_DEVICE_QSPI 0x02
> #define BOOT_DEVICE_SPI 0x03
> +#define BOOT_DEVICE_PCIE 0x03
> #define BOOT_DEVICE_CPGMAC 0x04
> #define BOOT_DEVICE_ETHERNET_RGMII 0x04
> #define BOOT_DEVICE_ETHERNET_RMII 0x05
> diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
> index 281fa3fea15..a828ad164f1 100644
> --- a/configs/am62x_evm_a53_defconfig
> +++ b/configs/am62x_evm_a53_defconfig
> @@ -1,4 +1,9 @@
> CONFIG_ARM=y
> +CONFIG_SPL_PCI_DFU=y
> +CONFIG_SPL_PCI_ENDPOINT=y
> +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x0
> +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x0
> +CONFIG_SPL_PCI_DFU_DEVICE_ID=0x0
> CONFIG_ARCH_K3=y
> CONFIG_SYS_MALLOC_F_LEN=0x8000
> CONFIG_TI_COMMON_CMD_OPTIONS=y
>
> The patch looks good to me and fixes the build warning :)
Thanks for the diff. This was very helpful to me.
I could reproduce using the default toolchains that are provided by
buildman [1] which is ~/.buildman-toolchains/gcc-14.2.0-nolibc
[1] https://docs.u-boot.org/en/latest/build/buildman.html
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # am62x_evm_a53
Will apply for master.
>
> Tested-by: Anshul Dalal <anshuld@ti.com>
>
>> ---
>>
>> Hello,
>>
>> This patch is based on commit
>> f473a453b0c kbuild: Drop phandle from diff between base DT and U-Boot augmented DT if DEVICE_TREE_DEBUG=1of the master branch of U-Boot.
>>
>> Regards,
>> Siddharth.
>>
>> common/spl/spl_dfu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c
>> index b09f82790c9..7d21bb4d16a 100644
>> --- a/common/spl/spl_dfu.c
>> +++ b/common/spl/spl_dfu.c
>> @@ -64,7 +64,7 @@ static int dfu_over_pcie(void)
>> hdr.deviceid = CONFIG_SPL_PCI_DFU_DEVICE_ID;
>> hdr.vendorid = CONFIG_SPL_PCI_DFU_VENDOR_ID;
>> hdr.baseclass_code = PCI_BASE_CLASS_MEMORY;
>> - hdr.subclass_code = PCI_CLASS_MEMORY_RAM;
>> + hdr.subclass_code = PCI_CLASS_MEMORY_RAM & 0xff;
>>
>> ret = pci_ep_write_header(dev, fn, &hdr);
>> if (ret) {
next prev parent reply other threads:[~2026-03-12 8:58 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-05 10:38 [PATCH] common: spl: spl_dfu.c: Fix warning associated with PCI subclass_code Siddharth Vadapalli
2026-03-05 13:08 ` Mattijs Korpershoek
2026-03-05 14:54 ` Siddharth Vadapalli
2026-03-06 5:04 ` Anshul Dalal
2026-03-12 8:58 ` Mattijs Korpershoek [this message]
2026-03-12 8:59 ` Mattijs Korpershoek
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