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Thu, 08 Jan 2026 04:47:45 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd0e175csm16161350f8f.14.2026.01.08.04.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 04:47:44 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 844D45F804; Thu, 08 Jan 2026 12:47:43 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: "Alano Song" Cc: "qemu-devel@nongnu.org" , "Jonathan Cameron" , "peter.maydell@linaro.org" , Joel Stanley , Chris Rauer Subject: Re: Question about qemu patch In-Reply-To: <331af4b3.96f0.19b9d487bf4.Coremail.alanosong@163.com> (Alano Song's message of "Thu, 8 Jan 2026 19:05:31 +0800 (CST)") References: <331af4b3.96f0.19b9d487bf4.Coremail.alanosong@163.com> User-Agent: mu4e 1.12.14; emacs 30.1 Date: Thu, 08 Jan 2026 12:47:43 +0000 Message-ID: <878qe89spc.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "Alano Song" writes: > Hi all, > > I am writing to share a patch and ask for some advice. > > I noticed there is no DesignWare I2C controller model in QEMU, > so I have attempted to add it: > https://lore.kernel.org/qemu-devel/20260106131253.16192-1-AlanoSong@163.c= om/ > > I have a couple of questions regarding the patch: > > 1) Is it acceptable to submit the I2C controller model by itself, > without instantiating it on any specific machine board? The problem with this approach is the code can very easily bitrot if it is not exercised by anything. We also tend to cull code that isn't used (for example if the old machine model was removed and we didn't notice at the time it was the only user of a device). > Users who need it could then add it to their own machine models. There is a long term aspiration to support dynamic machine models so they can be defined with some sort of Domain Specific Language (DSL). Until we reach that state we can only support devices used by machine models in the upstream. > 1.1) If it is required to instantiate the new model on a machine boar= d, > which board would you recommend for this purpose? > > Patch reviewer remained me, that the arm/virt board is a main mod= el used. > And I don't want make troubles on such important model. virt is a poor choice for as it is the main platform for virtualisation so adding extra devices just increases the potential surface area for security exploits. Ideally you would find a real machine that uses the IP and model that board. Looking at Zephyr it doesn't look like there are any existing QEMU models missing it: https://docs.zephyrproject.org/latest/boards/index.html#show-shields=3Dfa= lse&compatibles=3Dsnps%2Cdesignware-i2c > > 2) Coincidentally, I found that Joel Stanley is doing the same work=EF=BC= =8CHAHA :) > https://lore.kernel.org/qemu-devel/20260106055658.209029-12-joel@jms.= id.au/ > > What should I do next, may be we can work together to submit such > model ? I would contact Joel/Chris (cc'd) and collaborate on getting the best of both patches. It looks like the patch is part of a larger series that ads a new machine which solves one of the problems. > > Best Regards, > Alano Song. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro