From: "Alex Bennée" <alex.bennee@linaro.org>
To: Bernhard Beschow <shentey@gmail.com>
Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH 2/2] target/i386/cpu: Fix small typo in comment
Date: Wed, 03 Jan 2024 09:07:51 +0000 [thread overview]
Message-ID: <878r56iy3c.fsf@draig.linaro.org> (raw)
In-Reply-To: <20240103084900.22856-3-shentey@gmail.com> (Bernhard Beschow's message of "Wed, 3 Jan 2024 09:49:00 +0100")
Bernhard Beschow <shentey@gmail.com> writes:
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> ---
> target/i386/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 95d5f16cd5..2ae271e9a1 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2179,7 +2179,7 @@ static const CPUCaches epyc_genoa_cache_info = {
> * Conceal VM entries from PT
> * Enable ENCLS exiting
> * Mode-based execute control (XS/XU)
> - s TSC scaling (Skylake Server and newer)
> + * TSC scaling (Skylake Server and newer)
> * GPA translation for PT (IceLake and newer)
> * User wait and pause
> * ENCLV exiting
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
prev parent reply other threads:[~2024-01-03 9:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 8:48 [PATCH 0/2] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled Bernhard Beschow
2024-01-03 8:48 ` [PATCH 1/2] hw/i386/x86: Fix PIC interrupt handling if APIC " Bernhard Beschow
2024-01-03 9:12 ` Alex Bennée
2024-01-03 17:36 ` Bernhard Beschow
2024-01-03 8:49 ` [PATCH 2/2] target/i386/cpu: Fix small typo in comment Bernhard Beschow
2024-01-03 9:07 ` Alex Bennée [this message]
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