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From: Thomas Gleixner <tglx@linutronix.de>
To: isaku.yamahata@intel.com, Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>, "H . Peter Anvin" <hpa@zytor.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
	erdemaktas@google.com, Connor Kuehl <ckuehl@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com,
	Xiaoyao Li <xiaoyao.li@intel.com>
Subject: Re: [RFC PATCH v3 02/59] x86/mtrr: mask out keyid bits from variable mtrr mask register
Date: Thu, 25 Nov 2021 18:03:49 +0100	[thread overview]
Message-ID: <878rxckw0a.ffs@tglx> (raw)
In-Reply-To: <draft-87fsrkmy2c.ffs@tglx>

On Thu, Nov 25 2021 at 09:36, Thomas Gleixner wrote:
>>  
>> +			if (boot_cpu_has(X86_FEATURE_TME)) {

cpu_feature_enabled() as Borislav pointed out several times already.

>> +				u64 tme_activate;
>> +
>> +				rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
>> +				if (TME_ACTIVATE_LOCKED(tme_activate) &&
>> +				    TME_ACTIVATE_ENABLED(tme_activate)) {
>> +					phys_addr -= TME_ACTIVATE_KEYID_BITS(tme_activate);
>> +				}
>> +			}
>>  			size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
>>  			size_and_mask = ~size_or_mask & 0xfffff00000ULL;
>>  		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&

       reply	other threads:[~2021-11-25 17:19 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <draft-87fsrkmy2c.ffs@tglx>
2021-11-25 17:03 ` Thomas Gleixner [this message]
2021-11-25  0:19 [RFC PATCH v3 00/59] KVM: X86: TDX support isaku.yamahata
2021-11-25  0:19 ` [RFC PATCH v3 02/59] x86/mtrr: mask out keyid bits from variable mtrr mask register isaku.yamahata

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