From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff
Date: Wed, 25 Aug 2021 11:53:35 +0300 [thread overview]
Message-ID: <878s0pgb1s.fsf@intel.com> (raw)
In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com>
On Thu, 15 Jul 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> A bunch of cleanups to the DPLL code.
There were a couple of nitpicks to be made, but meh. Overall nice
cleanups.
One of the patches needed git am -C 0 to apply, please double check the
result if you resort to that while applying.
The series is
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Ville Syrjälä (13):
> drm/i915: Set output_types to EDP for vlv/chv DPLL forcing
> drm/i915: Clean up gen2 DPLL readout
> drm/i915: Extract ilk_update_pll_dividers()
> drm/i915: Constify struct dpll all over
> drm/i915: Clean dpll calling convention
> drm/i915: Clean up variable names in old dpll functions
> drm/i915: Remove the 'reg' local variable
> drm/i915: Program DPLL P1 dividers consistently
> drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()
> drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well
> drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()
> drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()
> drm/i915: Nuke intel_prepare_shared_dpll()
>
> drivers/gpu/drm/i915/display/intel_display.c | 42 +-
> .../drm/i915/display/intel_display_types.h | 5 -
> drivers/gpu/drm/i915/display/intel_dpll.c | 567 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll.h | 23 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 11 -
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> 7 files changed, 315 insertions(+), 377 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
prev parent reply other threads:[~2021-08-25 8:53 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 9:35 [Intel-gfx] [PATCH 00/13] drm/i915: Clean up DPLL stuff Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 02/13] drm/i915: Clean up gen2 DPLL readout Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 03/13] drm/i915: Extract ilk_update_pll_dividers() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 04/13] drm/i915: Constify struct dpll all over Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 06/13] drm/i915: Clean up variable names in old dpll functions Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 07/13] drm/i915: Remove the 'reg' local variable Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() Ville Syrjala
2021-07-15 9:35 ` [Intel-gfx] [PATCH 13/13] drm/i915: Nuke intel_prepare_shared_dpll() Ville Syrjala
2021-07-16 18:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up DPLL stuff Patchwork
2021-07-16 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17 0:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-08-25 8:53 ` Jani Nikula [this message]
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