From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabiano Rosas Date: Wed, 30 Jun 2021 19:41:40 +0000 Subject: Re: [RFC PATCH 07/43] KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests Message-Id: <878s2r2l8r.fsf@linux.ibm.com> List-Id: References: <20210622105736.633352-1-npiggin@gmail.com> <20210622105736.633352-8-npiggin@gmail.com> In-Reply-To: <20210622105736.633352-8-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Nicholas Piggin , kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Nicholas Piggin writes: > HV interrupts may be taken with the MMU enabled when radix guests are > running. Enable LPCR[HAIL] on ISA v3.1 processors for radix guests. > Make this depend on the host LPCR[HAIL] being enabled. Currently that is > always enabled, but having this test means any issue that might require > LPCR[HAIL] to be disabled in the host will not have to be duplicated in > KVM. > > -1380 cycles on P10 NULL hcall entry+exit > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv.c | 29 +++++++++++++++++++++++++---- > 1 file changed, 25 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 36e1db48fccf..ed713f49fbd5 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -4896,6 +4896,8 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu) > */ > int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > { > + unsigned long lpcr, lpcr_mask; > + > if (nesting_enabled(kvm)) > kvmhv_release_all_nested(kvm); > kvmppc_rmap_reset(kvm); > @@ -4905,8 +4907,13 @@ int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > kvm->arch.radix = 0; > spin_unlock(&kvm->mmu_lock); > kvmppc_free_radix(kvm); > - kvmppc_update_lpcr(kvm, LPCR_VPM1, > - LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR); > + > + lpcr = LPCR_VPM1; > + lpcr_mask = LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_ARCH_31)) > + lpcr_mask |= LPCR_HAIL; > + kvmppc_update_lpcr(kvm, lpcr, lpcr_mask); > + > return 0; > } > > @@ -4916,6 +4923,7 @@ int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > */ > int kvmppc_switch_mmu_to_radix(struct kvm *kvm) > { > + unsigned long lpcr, lpcr_mask; > int err; > > err = kvmppc_init_vm_radix(kvm); > @@ -4927,8 +4935,17 @@ int kvmppc_switch_mmu_to_radix(struct kvm *kvm) > kvm->arch.radix = 1; > spin_unlock(&kvm->mmu_lock); > kvmppc_free_hpt(&kvm->arch.hpt); > - kvmppc_update_lpcr(kvm, LPCR_UPRT | LPCR_GTSE | LPCR_HR, > - LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR); > + > + lpcr = LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + lpcr_mask = LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_ARCH_31)) { > + lpcr_mask |= LPCR_HAIL; > + if (cpu_has_feature(CPU_FTR_HVMODE) && > + (kvm->arch.host_lpcr & LPCR_HAIL)) > + lpcr |= LPCR_HAIL; > + } > + kvmppc_update_lpcr(kvm, lpcr, lpcr_mask); > + > return 0; > } > > @@ -5092,6 +5109,10 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm) > kvm->arch.mmu_ready = 1; > lpcr &= ~LPCR_VPM1; > lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_HVMODE) && > + cpu_has_feature(CPU_FTR_ARCH_31) && > + (kvm->arch.host_lpcr & LPCR_HAIL)) > + lpcr |= LPCR_HAIL; > ret = kvmppc_init_vm_radix(kvm); > if (ret) { > kvmppc_free_lpid(kvm->arch.lpid); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EDA3C11F69 for ; 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Wed, 30 Jun 2021 19:41:42 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , kvm-ppc@vger.kernel.org Subject: Re: [RFC PATCH 07/43] KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests In-Reply-To: <20210622105736.633352-8-npiggin@gmail.com> References: <20210622105736.633352-1-npiggin@gmail.com> <20210622105736.633352-8-npiggin@gmail.com> Date: Wed, 30 Jun 2021 16:41:40 -0300 Message-ID: <878s2r2l8r.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Ce5oA2nd1OMFIAw7Hoa4Fhh1uLK9YYMn X-Proofpoint-GUID: jpgS7y2wnVaaoUayAtXJGki2Lbg-Gk5T X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-30_08:2021-06-30, 2021-06-30 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 adultscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106300108 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > HV interrupts may be taken with the MMU enabled when radix guests are > running. Enable LPCR[HAIL] on ISA v3.1 processors for radix guests. > Make this depend on the host LPCR[HAIL] being enabled. Currently that is > always enabled, but having this test means any issue that might require > LPCR[HAIL] to be disabled in the host will not have to be duplicated in > KVM. > > -1380 cycles on P10 NULL hcall entry+exit > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv.c | 29 +++++++++++++++++++++++++---- > 1 file changed, 25 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 36e1db48fccf..ed713f49fbd5 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -4896,6 +4896,8 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu) > */ > int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > { > + unsigned long lpcr, lpcr_mask; > + > if (nesting_enabled(kvm)) > kvmhv_release_all_nested(kvm); > kvmppc_rmap_reset(kvm); > @@ -4905,8 +4907,13 @@ int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > kvm->arch.radix = 0; > spin_unlock(&kvm->mmu_lock); > kvmppc_free_radix(kvm); > - kvmppc_update_lpcr(kvm, LPCR_VPM1, > - LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR); > + > + lpcr = LPCR_VPM1; > + lpcr_mask = LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_ARCH_31)) > + lpcr_mask |= LPCR_HAIL; > + kvmppc_update_lpcr(kvm, lpcr, lpcr_mask); > + > return 0; > } > > @@ -4916,6 +4923,7 @@ int kvmppc_switch_mmu_to_hpt(struct kvm *kvm) > */ > int kvmppc_switch_mmu_to_radix(struct kvm *kvm) > { > + unsigned long lpcr, lpcr_mask; > int err; > > err = kvmppc_init_vm_radix(kvm); > @@ -4927,8 +4935,17 @@ int kvmppc_switch_mmu_to_radix(struct kvm *kvm) > kvm->arch.radix = 1; > spin_unlock(&kvm->mmu_lock); > kvmppc_free_hpt(&kvm->arch.hpt); > - kvmppc_update_lpcr(kvm, LPCR_UPRT | LPCR_GTSE | LPCR_HR, > - LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR); > + > + lpcr = LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + lpcr_mask = LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_ARCH_31)) { > + lpcr_mask |= LPCR_HAIL; > + if (cpu_has_feature(CPU_FTR_HVMODE) && > + (kvm->arch.host_lpcr & LPCR_HAIL)) > + lpcr |= LPCR_HAIL; > + } > + kvmppc_update_lpcr(kvm, lpcr, lpcr_mask); > + > return 0; > } > > @@ -5092,6 +5109,10 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm) > kvm->arch.mmu_ready = 1; > lpcr &= ~LPCR_VPM1; > lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; > + if (cpu_has_feature(CPU_FTR_HVMODE) && > + cpu_has_feature(CPU_FTR_ARCH_31) && > + (kvm->arch.host_lpcr & LPCR_HAIL)) > + lpcr |= LPCR_HAIL; > ret = kvmppc_init_vm_radix(kvm); > if (ret) { > kvmppc_free_lpid(kvm->arch.lpid);