Re: [Intel-gfx] [PATCH 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

From: Jani Nikula <jani.nikula@linux.intel.com>
To: Vipin Anand <vipin.anand@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON
Date: Tue, 07 Apr 2020 15:40:36 +0300	[thread overview]
Message-ID: <878sj7jwor.fsf@intel.com> (raw)
In-Reply-To: <20200327052357.22269-7-vipin.anand@intel.com>

On Fri, 27 Mar 2020, Vipin Anand <vipin.anand@intel.com> wrote:
> From: Uma Shankar <uma.shankar@intel.com>
>
> Blanking needs to be reduced to incorporate DP and HDMI timing/link
> bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
> 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
> This will cause mode to blank out. Reduced Htotal by shortening the
> back porch and front porch within permissible limits.
>
> v2: This is marked as Not for merge and the responsibilty to program
> these custom timings will be on userspace. This patch is just for
> reference purposes. This is based on Ville's recommendation.

This must be highlighted in the subject. HACK or whatever.

And even as a hack, don't change stuff in the .mode_valid hook. It
belongs to compute config.

BR,
Jani.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c7424e2a04a3..3ab1fadb2ea3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -616,9 +616,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  {
>  	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
>  	struct intel_connector *intel_connector = to_intel_connector(connector);
> +	struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
>  	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
>  	struct drm_i915_private *dev_priv = to_i915(connector->dev);
>  	int target_clock = mode->clock;
> +	struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>  	int max_dotclk;
>  	u16 dsc_max_output_bpp = 0;
> @@ -638,6 +640,20 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  
>  		target_clock = fixed_mode->clock;
>  	}
> +	/*
> +	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
> +	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
> +	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
> +	 * cause mode to blank out. Reduced Htotal by shortening the back porch
> +	 * and front porch within permissible limits.
> +	 */
> +	if (lspcon->active && lspcon->hdr_supported &&
> +	    mode->clock > 570000) {
> +		mode->clock = 570000;
> +		mode->htotal -= 180;
> +		mode->hsync_start -= 72;
> +		mode->hsync_end -= 72;
> +	}
>  
>  	max_link_clock = intel_dp_max_link_rate(intel_dp);
>  	max_lanes = intel_dp_max_lane_count(intel_dp);

-- 
Jani Nikula, Intel Open Source Graphics Center
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