From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Oscar Mateo <oscar.mateo@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [RFC PATCH 1/6] drm/i915: Remove Gen9 WAs with no effect
Date: Thu, 09 Nov 2017 13:42:45 +0200 [thread overview]
Message-ID: <878tffsmoa.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1510185589-9100-2-git-send-email-oscar.mateo@intel.com>
Oscar Mateo <oscar.mateo@intel.com> writes:
> GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
> the BIOS, so there is no way we can enable the three chicken bits
> mandated by the WA (the BIOS should be doing it instead).
>
> v2: Rebased
> v3: Standalone patch
>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> drivers/gpu/drm/i915/intel_pm.c | 3 ---
> 2 files changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f0f8f60..7991d90 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -355,9 +355,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
> #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
>
> -#define GEN8_CONFIG0 _MMIO(0xD00)
> -#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
> -
> #define GAC_ECO_BITS _MMIO(0x14090)
> #define ECOBITS_SNB_BIT (1<<13)
> #define ECOBITS_PPGTT_CACHE64B (3<<8)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e09377d..5bd49a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -75,9 +75,6 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_PAR1_1,
> I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>
> - I915_WRITE(GEN8_CONFIG0,
> - I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
> -
I am pondering if we should do a verifying read for workarounds
and chickens in general.
Also my kbl bios seem to omit all of these with lock being on :P
Patch is,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
-Mika
> /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> I915_WRITE(GEN8_CHICKEN_DCPR_1,
> I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> --
> 1.9.1
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next prev parent reply other threads:[~2017-11-09 11:42 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-08 23:59 [RFC PATCH v6 0/6] Refactor HW workaround code Oscar Mateo
2017-11-08 23:59 ` [RFC PATCH 1/6] drm/i915: Remove Gen9 WAs with no effect Oscar Mateo
2017-11-09 11:42 ` Mika Kuoppala [this message]
2017-11-09 11:48 ` Chris Wilson
2017-11-12 14:35 ` Chris Wilson
2017-11-08 23:59 ` [RFC PATCH 2/6] drm/i915: Move a bunch of workaround-related code to its own file Oscar Mateo
2017-11-08 23:59 ` [RFC PATCH 3/6] drm/i915: Split out functions for different kinds of workarounds Oscar Mateo
2017-11-08 23:59 ` [RFC PATCH 4/6] drm/i915: Move WA BB stuff to the workarounds file as well Oscar Mateo
2017-11-08 23:59 ` [RFC PATCH 5/6] drm/i915: Create a new category of display WAs Oscar Mateo
2017-11-08 23:59 ` [RFC PATCH 6/6] drm/i915: Classify GT & Display WAs correctly Oscar Mateo
2017-11-09 0:19 ` ✓ Fi.CI.BAT: success for Refactor HW workaround code (rev7) Patchwork
2017-11-09 1:11 ` ✓ Fi.CI.IGT: " Patchwork
2017-11-09 13:43 ` [RFC PATCH v6 0/6] Refactor HW workaround code Ville Syrjälä
2017-11-11 0:25 ` Oscar Mateo
2018-02-01 9:32 ` Chris Wilson
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