[PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[Mika Kuoppala]

We were pointing the color calc and depth stencil states blindly
to an offset of 1k from bb start. This was foolhardy as it collides
with other state in the batch and results in a wrecked state upload.

Chris noticed that with snb gt1, it takes 10 seconds for renderstate batch
to complete. However pointing the states to a known valid 64 aligned
zero blocks didn't work to reduce the upload time either.

Cave in and omit uploading color calc and depth stencil states.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 tools/null_state_gen/intel_renderstate_gen6.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c
index 5c1b7f97..c64e17fd 100644
--- a/tools/null_state_gen/intel_renderstate_gen6.c
+++ b/tools/null_state_gen/intel_renderstate_gen6.c
@@ -221,8 +221,10 @@ gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
 {
 	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
 	OUT_BATCH_STATE_OFFSET(blend | 1);
-	OUT_BATCH(1024 | 1);
-	OUT_BATCH(1024 | 1);
+	/* no color calc */
+	OUT_BATCH(0);
+	/* no depth stencil */
+	OUT_BATCH(0);
 }
 
 static void
-- 
2.11.0

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Re: [PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[Mika Kuoppala]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> We were pointing the color calc and depth stencil states blindly
> to an offset of 1k from bb start. This was foolhardy as it collides
> with other state in the batch and results in a wrecked state upload.
>
> Chris noticed that with snb gt1, it takes 10 seconds for renderstate batch
> to complete. However pointing the states to a known valid 64 aligned
> zero blocks didn't work to reduce the upload time either.
>
> Cave in and omit uploading color calc and depth stencil states.

Not just yet, ignore this patch.

>
> Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  tools/null_state_gen/intel_renderstate_gen6.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c
> index 5c1b7f97..c64e17fd 100644
> --- a/tools/null_state_gen/intel_renderstate_gen6.c
> +++ b/tools/null_state_gen/intel_renderstate_gen6.c
> @@ -221,8 +221,10 @@ gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
>  {
>  	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
>  	OUT_BATCH_STATE_OFFSET(blend | 1);
> -	OUT_BATCH(1024 | 1);
> -	OUT_BATCH(1024 | 1);
> +	/* no color calc */
> +	OUT_BATCH(0);
> +	/* no depth stencil */
> +	OUT_BATCH(0);
>  }
>  
>  static void
> -- 
> 2.11.0
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Re: [PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[Chris Wilson]

Quoting Mika Kuoppala (2017-08-08 14:36:59)
> Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
> 
> > We were pointing the color calc and depth stencil states blindly
> > to an offset of 1k from bb start. This was foolhardy as it collides
> > with other state in the batch and results in a wrecked state upload.
> >
> > Chris noticed that with snb gt1, it takes 10 seconds for renderstate batch
> > to complete. However pointing the states to a known valid 64 aligned
> > zero blocks didn't work to reduce the upload time either.
> >
> > Cave in and omit uploading color calc and depth stencil states.
> 
> Not just yet, ignore this patch.

Right, we found the root cause for my issue, so we can actually load the
correct state here (i.e. create a NUL block and point both depth-stencil
and color-calc to it). We could use that same block for the blend state
as well, etc.
-Chris
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Re: [PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2017-08-08 14:36:59)
>> Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
>> 
>> > We were pointing the color calc and depth stencil states blindly
>> > to an offset of 1k from bb start. This was foolhardy as it collides
>> > with other state in the batch and results in a wrecked state upload.
>> >
>> > Chris noticed that with snb gt1, it takes 10 seconds for renderstate batch
>> > to complete. However pointing the states to a known valid 64 aligned
>> > zero blocks didn't work to reduce the upload time either.
>> >
>> > Cave in and omit uploading color calc and depth stencil states.
>> 
>> Not just yet, ignore this patch.
>
> Right, we found the root cause for my issue, so we can actually load the
> correct state here (i.e. create a NUL block and point both depth-stencil
> and color-calc to it). We could use that same block for the blend state
> as well, etc.

I chose to keep the blend state as is, for the first step. As the blend
state is is not all zeros. But after the patch to add cc and depth
stencil states as null, it is a minor step, as in code, to nullify the
blend state also.

-Mika

> -Chris
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✓ Fi.CI.BAT: success for tools/null_state_gen: Don't upload color calc and depth stencil on gen6

[Patchwork]

== Series Details ==

Series: tools/null_state_gen: Don't upload color calc and depth stencil on gen6
URL   : https://patchwork.freedesktop.org/series/28496/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
eeff6a1d9c4e2c195b30ad95ee36a58ef6ca3387 intel_gpu_top: Use drm_open_driver, don't need drm master

with latest DRM-Tip kernel build CI_DRM_2933
9d6913ce7311 drm-tip: 2017y-08m-08d-12h-52m-33s UTC integration manifest

Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:440s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:424s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:356s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:484s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:492s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:520s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:513s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:584s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:426s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:409s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:411s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:511s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:479s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:457s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:568s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:574s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:524s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:454s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:640s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:459s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:431s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:482s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:548s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:413s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_31/
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