From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44001) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4tlD-00020M-Qj for qemu-devel@nongnu.org; Thu, 10 Nov 2016 13:07:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4tlA-0003H5-NQ for qemu-devel@nongnu.org; Thu, 10 Nov 2016 13:07:39 -0500 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:38738) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c4tlA-0003G9-8N for qemu-devel@nongnu.org; Thu, 10 Nov 2016 13:07:36 -0500 Received: by mail-wm0-x22f.google.com with SMTP id f82so48103219wmf.1 for ; Thu, 10 Nov 2016 10:07:36 -0800 (PST) References: <20161109145748.27282-1-alex.bennee@linaro.org> <20161109145748.27282-14-alex.bennee@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Thu, 10 Nov 2016 18:07:33 +0000 Message-ID: <878tsr8aze.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v6 13/19] cputlb: atomically update tlb fields used by tlb_reset_dirty List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mttcg@greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite Richard Henderson writes: > On 11/09/2016 03:57 PM, Alex Bennée wrote: >> +/* We currently can't handle more than 16 bits in the MMUIDX bitmask. >> + */ >> +QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); > > We already assert <= 12 in exec/cpu_ldst.h. Although really any such assert > belongs in exec/cpu-defs.h, where we define CPU_TLB_BITS et al. > > That said, what's the technical restriction here? Really we just need to ensure that we don't run out of bits to convert the MMUIDX var args into the bottom bit of a page aligned address. We already have: QEMU_BUILD_BUG_ON(NB_MMU_MODES > TARGET_PAGE_BITS_MIN); So I guess I can drop the other one. -- Alex Bennée