From: Felipe Balbi <balbi@kernel.org>
To: Rob Herring <robh@kernel.org>, John Youn <johnyoun@synopsys.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Thinh Nguyen <thinhn@synopsys.com>
Subject: Re: [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register
Date: Tue, 13 Sep 2016 08:46:49 +0300 [thread overview]
Message-ID: <878tuwl5bq.fsf@linux.intel.com> (raw)
In-Reply-To: <20160912153018.GA14561@rob-hp-laptop>
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Hi,
Rob Herring <robh@kernel.org> writes:
>> Synopsys HW setup (HAPS DX and phy board) requires a preset to this
>> register to improve interoperablitity. For example, the value for
>> GFLADJ_REFCLK_LPM_SEL should be set to 0 with ref_clk period of 50.
>
> This sounds like it should be handled in the driver. Is it a simple,
> constant correlation of ref_clk period to this value?
you mean that this could be calculated based off of clk_get_rate() ?
--
balbi
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next prev parent reply other threads:[~2016-09-13 5:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-01 21:32 [PATCH 1/2] usb: dwc3: Add ref clock period setting John Youn
2016-09-01 21:32 ` John Youn
[not found] ` <ae2c9b5683820c6456f91a2ef631efa2de0bec28.1472764828.git.johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
2016-09-01 21:32 ` [PATCH 2/2] usb: dwc3: Added a property to set GFLADJ register John Youn
2016-09-01 21:32 ` John Youn
2016-09-01 21:32 ` John Youn
2016-09-12 15:30 ` Rob Herring
2016-09-13 5:46 ` Felipe Balbi [this message]
2016-09-13 19:12 ` John Youn
2016-09-13 19:12 ` John Youn
2016-09-12 14:09 ` [PATCH 1/2] usb: dwc3: Add ref clock period setting Rob Herring
2016-09-12 14:09 ` Rob Herring
2016-09-13 19:06 ` John Youn
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