From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Date: Mon, 13 Jun 2016 10:40:31 +0000 Subject: Re: [patch] drm/i915/mocs: || vs | typo in get_mocs_settings() Message-Id: <878ty9xtgg.fsf@intel.com> List-Id: References: <20160613065422.GB5993@mwanda> In-Reply-To: <20160613065422.GB5993@mwanda> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Dan Carpenter , Daniel Vetter Cc: David Airlie , intel-gfx@lists.freedesktop.org, kernel-janitors@vger.kernel.org, dri-devel@lists.freedesktop.org Dan Carpenter writes: > It seems pretty clear that bitwise OR was intended here and not logical > OR. > > Fixes: 6fc29133eafb ('drm/i915/gen9: Add WaDisableSkipCaching') > Signed-off-by: Dan Carpenter Reviewed-by: Mika Kuoppala > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 8f96c40..3c1482b 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -162,7 +162,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > > for (i = 0; i < table->size; i++) > if (WARN_ON(table->table[i].l3cc_value & > - (L3_ESC(1) || L3_SCC(0x7)))) > + (L3_ESC(1) | L3_SCC(0x7)))) > return false; > } > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [patch] drm/i915/mocs: || vs | typo in get_mocs_settings() Date: Mon, 13 Jun 2016 13:40:31 +0300 Message-ID: <878ty9xtgg.fsf@intel.com> References: <20160613065422.GB5993@mwanda> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20160613065422.GB5993@mwanda> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Dan Carpenter , Daniel Vetter Cc: David Airlie , intel-gfx@lists.freedesktop.org, kernel-janitors@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org RGFuIENhcnBlbnRlciA8ZGFuLmNhcnBlbnRlckBvcmFjbGUuY29tPiB3cml0ZXM6Cgo+IEl0IHNl ZW1zIHByZXR0eSBjbGVhciB0aGF0IGJpdHdpc2UgT1Igd2FzIGludGVuZGVkIGhlcmUgYW5kIG5v dCBsb2dpY2FsCj4gT1IuCj4KPiBGaXhlczogNmZjMjkxMzNlYWZiICgnZHJtL2k5MTUvZ2VuOTog QWRkIFdhRGlzYWJsZVNraXBDYWNoaW5nJykKPiBTaWduZWQtb2ZmLWJ5OiBEYW4gQ2FycGVudGVy IDxkYW4uY2FycGVudGVyQG9yYWNsZS5jb20+CgpSZXZpZXdlZC1ieTogTWlrYSBLdW9wcGFsYSA8 bWlrYS5rdW9wcGFsYUBpbnRlbC5jb20+Cgo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2ludGVsX21vY3MuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX21vY3MuYwo+ IGluZGV4IDhmOTZjNDAuLjNjMTQ4MmIgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5 MTUvaW50ZWxfbW9jcy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfbW9jcy5j Cj4gQEAgLTE2Miw3ICsxNjIsNyBAQCBzdGF0aWMgYm9vbCBnZXRfbW9jc19zZXR0aW5ncyhzdHJ1 Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCj4gIAo+ICAJCWZvciAoaSA9IDA7IGkgPCB0 YWJsZS0+c2l6ZTsgaSsrKQo+ICAJCQlpZiAoV0FSTl9PTih0YWJsZS0+dGFibGVbaV0ubDNjY192 YWx1ZSAmCj4gLQkJCQkgICAgKEwzX0VTQygxKSB8fCBMM19TQ0MoMHg3KSkpKQo+ICsJCQkJICAg IChMM19FU0MoMSkgfCBMM19TQ0MoMHg3KSkpKQo+ICAJCQkJcmV0dXJuIGZhbHNlOwo+ICAJfQo+ ICAKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwt Z2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==