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[46.27.169.188]) by smtp.gmail.com with ESMTPSA id u10sm2093058wmj.40.2021.02.10.04.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Feb 2021 04:14:25 -0800 (PST) Subject: Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 To: Enric Balletbo Serra , Hsin-Yi Wang References: <20210129092209.2584718-1-hsinyi@chromium.org> <20210129092209.2584718-8-hsinyi@chromium.org> From: Matthias Brugger Message-ID: <879e6699-75c1-476b-8114-83b97fd4e00a@gmail.com> Date: Wed, 10 Feb 2021 13:14:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_071427_434319_CFA4457B X-CRM114-Status: GOOD ( 25.04 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "devicetree@vger.kernel.org" , Philipp Zabel , David Airlie , linux-kernel , dri-devel , "moderated list:ARM/Mediatek SoC support" , Yongqiang Niu , CK Hu , Daniel Vetter , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 09/02/2021 15:48, Enric Balletbo Serra wrote: > Hi Hsin-Yi, > > Thank you for your patch. > > Missatge de Hsin-Yi Wang del dia dv., 29 de gen. > 2021 a les 10:23: >> >> From: Yongqiang Niu >> >> Add mtk mutex support for MT8183 SoC. >> >> Signed-off-by: Yongqiang Niu >> Signed-off-by: Hsin-Yi Wang >> Reviewed-by: CK Hu > > Reviewed-by: Enric Balletbo i Serra > > FWIW this patch is required to have the display working on the > Chromebook IdeaPad Duet, so > > Tested-by: Enric Balletbo i Serra > > Matthias, If I am not wrong, this patch is the only one that is not > applied for this series. I know that is too late for 5.12, but If > you're fine with it, could you pick this patch directly or do you > prefer a resend of this patch alone once you will start to accept > patches for the next release? This patch is based on top of a patch that's in CK's branch. Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC Regards, Matthias > > Thanks, > Enric > >> --- >> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c >> index f531b119da7a9..718a41beb6afb 100644 >> --- a/drivers/soc/mediatek/mtk-mutex.c >> +++ b/drivers/soc/mediatek/mtk-mutex.c >> @@ -14,6 +14,8 @@ >> >> #define MT2701_MUTEX0_MOD0 0x2c >> #define MT2701_MUTEX0_SOF0 0x30 >> +#define MT8183_MUTEX0_MOD0 0x30 >> +#define MT8183_MUTEX0_SOF0 0x2c >> >> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) >> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) >> @@ -37,6 +39,18 @@ >> #define MT8167_MUTEX_MOD_DISP_DITHER 15 >> #define MT8167_MUTEX_MOD_DISP_UFOE 16 >> >> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 >> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 >> +#define MT8183_MUTEX_MOD_DISP_OVL0 9 >> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 >> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 >> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 >> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 >> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 >> +#define MT8183_MUTEX_MOD_DISP_AAL0 15 >> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 >> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 >> + >> #define MT8173_MUTEX_MOD_DISP_OVL0 11 >> #define MT8173_MUTEX_MOD_DISP_OVL1 12 >> #define MT8173_MUTEX_MOD_DISP_RDMA0 13 >> @@ -87,6 +101,11 @@ >> #define MT2712_MUTEX_SOF_DSI3 6 >> #define MT8167_MUTEX_SOF_DPI0 2 >> #define MT8167_MUTEX_SOF_DPI1 3 >> +#define MT8183_MUTEX_SOF_DSI0 1 >> +#define MT8183_MUTEX_SOF_DPI0 2 >> + >> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) >> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) >> >> struct mtk_mutex { >> int id; >> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, >> }; >> >> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, >> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, >> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, >> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, >> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, >> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, >> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, >> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, >> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, >> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, >> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, >> +}; >> + >> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, >> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, >> }; >> >> +/* Add EOF setting so overlay hardware can receive frame done irq */ >> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, >> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, >> +}; >> + >> static const struct mtk_mutex_data mt2701_mutex_driver_data = { >> .mutex_mod = mt2701_mutex_mod, >> .mutex_sof = mt2712_mutex_sof, >> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { >> .mutex_sof_reg = MT2701_MUTEX0_SOF0, >> }; >> >> +static const struct mtk_mutex_data mt8183_mutex_driver_data = { >> + .mutex_mod = mt8183_mutex_mod, >> + .mutex_sof = mt8183_mutex_sof, >> + .mutex_mod_reg = MT8183_MUTEX0_MOD0, >> + .mutex_sof_reg = MT8183_MUTEX0_SOF0, >> + .no_clk = true, >> +}; >> + >> struct mtk_mutex *mtk_mutex_get(struct device *dev) >> { >> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); >> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { >> .data = &mt8167_mutex_driver_data}, >> { .compatible = "mediatek,mt8173-disp-mutex", >> .data = &mt8173_mutex_driver_data}, >> + { .compatible = "mediatek,mt8183-disp-mutex", >> + .data = &mt8183_mutex_driver_data}, >> {}, >> }; >> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); >> -- >> 2.30.0.365.g02bc693789-goog >> >> >> _______________________________________________ >> Linux-mediatek mailing list >> Linux-mediatek@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72E0FC433DB for ; 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[46.27.169.188]) by smtp.gmail.com with ESMTPSA id u10sm2093058wmj.40.2021.02.10.04.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Feb 2021 04:14:25 -0800 (PST) Subject: Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 To: Enric Balletbo Serra , Hsin-Yi Wang References: <20210129092209.2584718-1-hsinyi@chromium.org> <20210129092209.2584718-8-hsinyi@chromium.org> From: Matthias Brugger Message-ID: <879e6699-75c1-476b-8114-83b97fd4e00a@gmail.com> Date: Wed, 10 Feb 2021 13:14:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_071427_434319_CFA4457B X-CRM114-Status: GOOD ( 25.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "devicetree@vger.kernel.org" , Philipp Zabel , David Airlie , linux-kernel , dri-devel , "moderated list:ARM/Mediatek SoC support" , Yongqiang Niu , CK Hu , Daniel Vetter , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/02/2021 15:48, Enric Balletbo Serra wrote: > Hi Hsin-Yi, > > Thank you for your patch. > > Missatge de Hsin-Yi Wang del dia dv., 29 de gen. > 2021 a les 10:23: >> >> From: Yongqiang Niu >> >> Add mtk mutex support for MT8183 SoC. >> >> Signed-off-by: Yongqiang Niu >> Signed-off-by: Hsin-Yi Wang >> Reviewed-by: CK Hu > > Reviewed-by: Enric Balletbo i Serra > > FWIW this patch is required to have the display working on the > Chromebook IdeaPad Duet, so > > Tested-by: Enric Balletbo i Serra > > Matthias, If I am not wrong, this patch is the only one that is not > applied for this series. I know that is too late for 5.12, but If > you're fine with it, could you pick this patch directly or do you > prefer a resend of this patch alone once you will start to accept > patches for the next release? This patch is based on top of a patch that's in CK's branch. Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC Regards, Matthias > > Thanks, > Enric > >> --- >> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c >> index f531b119da7a9..718a41beb6afb 100644 >> --- a/drivers/soc/mediatek/mtk-mutex.c >> +++ b/drivers/soc/mediatek/mtk-mutex.c >> @@ -14,6 +14,8 @@ >> >> #define MT2701_MUTEX0_MOD0 0x2c >> #define MT2701_MUTEX0_SOF0 0x30 >> +#define MT8183_MUTEX0_MOD0 0x30 >> +#define MT8183_MUTEX0_SOF0 0x2c >> >> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) >> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) >> @@ -37,6 +39,18 @@ >> #define MT8167_MUTEX_MOD_DISP_DITHER 15 >> #define MT8167_MUTEX_MOD_DISP_UFOE 16 >> >> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 >> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 >> +#define MT8183_MUTEX_MOD_DISP_OVL0 9 >> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 >> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 >> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 >> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 >> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 >> +#define MT8183_MUTEX_MOD_DISP_AAL0 15 >> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 >> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 >> + >> #define MT8173_MUTEX_MOD_DISP_OVL0 11 >> #define MT8173_MUTEX_MOD_DISP_OVL1 12 >> #define MT8173_MUTEX_MOD_DISP_RDMA0 13 >> @@ -87,6 +101,11 @@ >> #define MT2712_MUTEX_SOF_DSI3 6 >> #define MT8167_MUTEX_SOF_DPI0 2 >> #define MT8167_MUTEX_SOF_DPI1 3 >> +#define MT8183_MUTEX_SOF_DSI0 1 >> +#define MT8183_MUTEX_SOF_DPI0 2 >> + >> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) >> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) >> >> struct mtk_mutex { >> int id; >> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, >> }; >> >> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, >> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, >> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, >> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, >> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, >> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, >> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, >> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, >> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, >> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, >> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, >> +}; >> + >> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, >> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, >> }; >> >> +/* Add EOF setting so overlay hardware can receive frame done irq */ >> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, >> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, >> +}; >> + >> static const struct mtk_mutex_data mt2701_mutex_driver_data = { >> .mutex_mod = mt2701_mutex_mod, >> .mutex_sof = mt2712_mutex_sof, >> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { >> .mutex_sof_reg = MT2701_MUTEX0_SOF0, >> }; >> >> +static const struct mtk_mutex_data mt8183_mutex_driver_data = { >> + .mutex_mod = mt8183_mutex_mod, >> + .mutex_sof = mt8183_mutex_sof, >> + .mutex_mod_reg = MT8183_MUTEX0_MOD0, >> + .mutex_sof_reg = MT8183_MUTEX0_SOF0, >> + .no_clk = true, >> +}; >> + >> struct mtk_mutex *mtk_mutex_get(struct device *dev) >> { >> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); >> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { >> .data = &mt8167_mutex_driver_data}, >> { .compatible = "mediatek,mt8173-disp-mutex", >> .data = &mt8173_mutex_driver_data}, >> + { .compatible = "mediatek,mt8183-disp-mutex", >> + .data = &mt8183_mutex_driver_data}, >> {}, >> }; >> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); >> -- >> 2.30.0.365.g02bc693789-goog >> >> >> _______________________________________________ >> Linux-mediatek mailing list >> Linux-mediatek@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E7CAC433E9 for ; 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[46.27.169.188]) by smtp.gmail.com with ESMTPSA id u10sm2093058wmj.40.2021.02.10.04.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Feb 2021 04:14:25 -0800 (PST) Subject: Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 To: Enric Balletbo Serra , Hsin-Yi Wang Cc: CK Hu , Philipp Zabel , Mark Rutland , "devicetree@vger.kernel.org" , Yongqiang Niu , David Airlie , linux-kernel , dri-devel , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , Linux ARM References: <20210129092209.2584718-1-hsinyi@chromium.org> <20210129092209.2584718-8-hsinyi@chromium.org> From: Matthias Brugger Message-ID: <879e6699-75c1-476b-8114-83b97fd4e00a@gmail.com> Date: Wed, 10 Feb 2021 13:14:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 09/02/2021 15:48, Enric Balletbo Serra wrote: > Hi Hsin-Yi, > > Thank you for your patch. > > Missatge de Hsin-Yi Wang del dia dv., 29 de gen. > 2021 a les 10:23: >> >> From: Yongqiang Niu >> >> Add mtk mutex support for MT8183 SoC. >> >> Signed-off-by: Yongqiang Niu >> Signed-off-by: Hsin-Yi Wang >> Reviewed-by: CK Hu > > Reviewed-by: Enric Balletbo i Serra > > FWIW this patch is required to have the display working on the > Chromebook IdeaPad Duet, so > > Tested-by: Enric Balletbo i Serra > > Matthias, If I am not wrong, this patch is the only one that is not > applied for this series. I know that is too late for 5.12, but If > you're fine with it, could you pick this patch directly or do you > prefer a resend of this patch alone once you will start to accept > patches for the next release? This patch is based on top of a patch that's in CK's branch. Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC Regards, Matthias > > Thanks, > Enric > >> --- >> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c >> index f531b119da7a9..718a41beb6afb 100644 >> --- a/drivers/soc/mediatek/mtk-mutex.c >> +++ b/drivers/soc/mediatek/mtk-mutex.c >> @@ -14,6 +14,8 @@ >> >> #define MT2701_MUTEX0_MOD0 0x2c >> #define MT2701_MUTEX0_SOF0 0x30 >> +#define MT8183_MUTEX0_MOD0 0x30 >> +#define MT8183_MUTEX0_SOF0 0x2c >> >> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) >> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) >> @@ -37,6 +39,18 @@ >> #define MT8167_MUTEX_MOD_DISP_DITHER 15 >> #define MT8167_MUTEX_MOD_DISP_UFOE 16 >> >> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 >> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 >> +#define MT8183_MUTEX_MOD_DISP_OVL0 9 >> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 >> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 >> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 >> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 >> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 >> +#define MT8183_MUTEX_MOD_DISP_AAL0 15 >> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 >> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 >> + >> #define MT8173_MUTEX_MOD_DISP_OVL0 11 >> #define MT8173_MUTEX_MOD_DISP_OVL1 12 >> #define MT8173_MUTEX_MOD_DISP_RDMA0 13 >> @@ -87,6 +101,11 @@ >> #define MT2712_MUTEX_SOF_DSI3 6 >> #define MT8167_MUTEX_SOF_DPI0 2 >> #define MT8167_MUTEX_SOF_DPI1 3 >> +#define MT8183_MUTEX_SOF_DSI0 1 >> +#define MT8183_MUTEX_SOF_DPI0 2 >> + >> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) >> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) >> >> struct mtk_mutex { >> int id; >> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, >> }; >> >> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, >> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, >> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, >> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, >> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, >> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, >> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, >> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, >> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, >> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, >> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, >> +}; >> + >> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, >> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, >> }; >> >> +/* Add EOF setting so overlay hardware can receive frame done irq */ >> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, >> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, >> +}; >> + >> static const struct mtk_mutex_data mt2701_mutex_driver_data = { >> .mutex_mod = mt2701_mutex_mod, >> .mutex_sof = mt2712_mutex_sof, >> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { >> .mutex_sof_reg = MT2701_MUTEX0_SOF0, >> }; >> >> +static const struct mtk_mutex_data mt8183_mutex_driver_data = { >> + .mutex_mod = mt8183_mutex_mod, >> + .mutex_sof = mt8183_mutex_sof, >> + .mutex_mod_reg = MT8183_MUTEX0_MOD0, >> + .mutex_sof_reg = MT8183_MUTEX0_SOF0, >> + .no_clk = true, >> +}; >> + >> struct mtk_mutex *mtk_mutex_get(struct device *dev) >> { >> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); >> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { >> .data = &mt8167_mutex_driver_data}, >> { .compatible = "mediatek,mt8173-disp-mutex", >> .data = &mt8173_mutex_driver_data}, >> + { .compatible = "mediatek,mt8183-disp-mutex", >> + .data = &mt8183_mutex_driver_data}, >> {}, >> }; >> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); >> -- >> 2.30.0.365.g02bc693789-goog >> >> >> _______________________________________________ >> Linux-mediatek mailing list >> Linux-mediatek@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3591C433E0 for ; Wed, 10 Feb 2021 12:14:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5F71864E2A for ; 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[46.27.169.188]) by smtp.gmail.com with ESMTPSA id u10sm2093058wmj.40.2021.02.10.04.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Feb 2021 04:14:25 -0800 (PST) Subject: Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 To: Enric Balletbo Serra , Hsin-Yi Wang References: <20210129092209.2584718-1-hsinyi@chromium.org> <20210129092209.2584718-8-hsinyi@chromium.org> From: Matthias Brugger Message-ID: <879e6699-75c1-476b-8114-83b97fd4e00a@gmail.com> Date: Wed, 10 Feb 2021 13:14:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "devicetree@vger.kernel.org" , David Airlie , linux-kernel , dri-devel , "moderated list:ARM/Mediatek SoC support" , Yongqiang Niu , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 09/02/2021 15:48, Enric Balletbo Serra wrote: > Hi Hsin-Yi, > > Thank you for your patch. > > Missatge de Hsin-Yi Wang del dia dv., 29 de gen. > 2021 a les 10:23: >> >> From: Yongqiang Niu >> >> Add mtk mutex support for MT8183 SoC. >> >> Signed-off-by: Yongqiang Niu >> Signed-off-by: Hsin-Yi Wang >> Reviewed-by: CK Hu > > Reviewed-by: Enric Balletbo i Serra > > FWIW this patch is required to have the display working on the > Chromebook IdeaPad Duet, so > > Tested-by: Enric Balletbo i Serra > > Matthias, If I am not wrong, this patch is the only one that is not > applied for this series. I know that is too late for 5.12, but If > you're fine with it, could you pick this patch directly or do you > prefer a resend of this patch alone once you will start to accept > patches for the next release? This patch is based on top of a patch that's in CK's branch. Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC Regards, Matthias > > Thanks, > Enric > >> --- >> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c >> index f531b119da7a9..718a41beb6afb 100644 >> --- a/drivers/soc/mediatek/mtk-mutex.c >> +++ b/drivers/soc/mediatek/mtk-mutex.c >> @@ -14,6 +14,8 @@ >> >> #define MT2701_MUTEX0_MOD0 0x2c >> #define MT2701_MUTEX0_SOF0 0x30 >> +#define MT8183_MUTEX0_MOD0 0x30 >> +#define MT8183_MUTEX0_SOF0 0x2c >> >> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) >> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) >> @@ -37,6 +39,18 @@ >> #define MT8167_MUTEX_MOD_DISP_DITHER 15 >> #define MT8167_MUTEX_MOD_DISP_UFOE 16 >> >> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 >> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 >> +#define MT8183_MUTEX_MOD_DISP_OVL0 9 >> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 >> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 >> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 >> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 >> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 >> +#define MT8183_MUTEX_MOD_DISP_AAL0 15 >> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 >> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 >> + >> #define MT8173_MUTEX_MOD_DISP_OVL0 11 >> #define MT8173_MUTEX_MOD_DISP_OVL1 12 >> #define MT8173_MUTEX_MOD_DISP_RDMA0 13 >> @@ -87,6 +101,11 @@ >> #define MT2712_MUTEX_SOF_DSI3 6 >> #define MT8167_MUTEX_SOF_DPI0 2 >> #define MT8167_MUTEX_SOF_DPI1 3 >> +#define MT8183_MUTEX_SOF_DSI0 1 >> +#define MT8183_MUTEX_SOF_DPI0 2 >> + >> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) >> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) >> >> struct mtk_mutex { >> int id; >> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, >> }; >> >> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { >> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, >> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, >> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, >> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, >> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, >> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, >> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, >> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, >> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, >> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, >> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, >> +}; >> + >> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, >> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, >> }; >> >> +/* Add EOF setting so overlay hardware can receive frame done irq */ >> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { >> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, >> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, >> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, >> +}; >> + >> static const struct mtk_mutex_data mt2701_mutex_driver_data = { >> .mutex_mod = mt2701_mutex_mod, >> .mutex_sof = mt2712_mutex_sof, >> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { >> .mutex_sof_reg = MT2701_MUTEX0_SOF0, >> }; >> >> +static const struct mtk_mutex_data mt8183_mutex_driver_data = { >> + .mutex_mod = mt8183_mutex_mod, >> + .mutex_sof = mt8183_mutex_sof, >> + .mutex_mod_reg = MT8183_MUTEX0_MOD0, >> + .mutex_sof_reg = MT8183_MUTEX0_SOF0, >> + .no_clk = true, >> +}; >> + >> struct mtk_mutex *mtk_mutex_get(struct device *dev) >> { >> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); >> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { >> .data = &mt8167_mutex_driver_data}, >> { .compatible = "mediatek,mt8173-disp-mutex", >> .data = &mt8173_mutex_driver_data}, >> + { .compatible = "mediatek,mt8183-disp-mutex", >> + .data = &mt8183_mutex_driver_data}, >> {}, >> }; >> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); >> -- >> 2.30.0.365.g02bc693789-goog >> >> >> _______________________________________________ >> Linux-mediatek mailing list >> Linux-mediatek@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel