From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915/dsi: Assert that vfp+vsync+vbp == vtotal on BXT/GLK
Date: Fri, 04 Apr 2025 16:21:51 +0300 [thread overview]
Message-ID: <87a58wyscw.fsf@intel.com> (raw)
In-Reply-To: <20250314150136.22564-3-ville.syrjala@linux.intel.com>
On Fri, 14 Mar 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Windows code seems to do some dodgy looking +/-1 adjustments
> to some of the vertical timings. Not sure if that's correct
> or not, but let's at least cross check some of the values
> we got from the hardware to double check whether the GOP
> did the same or not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/vlv_dsi.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 661de51dfd22..cdab04727c7d 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1024,7 +1024,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> unsigned int lane_count = intel_dsi->lane_count;
> unsigned int bpp, fmt;
> enum port port;
> - u16 hactive, hfp, hsync, hbp, vfp, vsync;
> + u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> u16 hfp_sw, hsync_sw, hbp_sw;
> u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
> crtc_hblank_start_sw, crtc_hblank_end_sw;
> @@ -1088,6 +1088,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>
> /* vertical values are in terms of lines */
> vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));
> + vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));
> vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));
>
> adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
> @@ -1096,6 +1097,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
>
> + drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay +
> + vfp + vsync + vbp != adjusted_mode->crtc_vtotal);
> adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
> adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
> adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-04-04 13:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-14 15:01 [PATCH 1/3] drm/i915/dsi: Fix off by one in BXT_MIPI_TRANS_VTOTAL Ville Syrjala
2025-03-14 15:01 ` [PATCH 2/3] drm/i915/dsi: Don't set/read the DSI C clock divider on GLK Ville Syrjala
2025-04-04 13:21 ` Jani Nikula
2025-03-14 15:01 ` [PATCH 3/3] drm/i915/dsi: Assert that vfp+vsync+vbp == vtotal on BXT/GLK Ville Syrjala
2025-04-04 13:21 ` Jani Nikula [this message]
2025-03-14 19:19 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dsi: Fix off by one in BXT_MIPI_TRANS_VTOTAL Patchwork
2025-03-14 19:19 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-14 19:41 ` ✓ i915.CI.BAT: success " Patchwork
2025-03-19 16:28 ` ✗ i915.CI.Full: failure " Patchwork
2025-04-04 13:13 ` [PATCH 1/3] " Jani Nikula
2025-04-04 13:14 ` Jani Nikula
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