From: Markus Armbruster <armbru@redhat.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
palmer@dabbelt.com, alistair.francis@wdc.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
richard.henderson@linaro.org, Swung0x48 <swung0x48@outlook.com>,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector
Date: Fri, 20 Sep 2024 13:37:34 +0200 [thread overview]
Message-ID: <87a5g2imip.fsf@pond.sub.org> (raw)
In-Reply-To: <e1ecceab-084e-4864-a361-e5f06fa4b57d@ventanamicro.com> (Daniel Henrique Barboza's message of "Fri, 20 Sep 2024 08:26:52 -0300")
Daniel Henrique Barboza <dbarboza@ventanamicro.com> writes:
> Hi Zhiwei,
>
> As Rixchard already pointed out, we must have a "Signed-off-by" tag with the "author" of
> the patch, and it must be the exact spelling. So in this case:
>
> Signed-off-by: Swung0x48 <swung0x48@outlook.com>
I'm afraid we need a legal name here, not a nickname.
> More info here:
>
> https://www.qemu.org/docs/master/devel/submitting-a-patch.html
[...]
next prev parent reply other threads:[~2024-09-20 11:38 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-11 13:26 [PATCH v4 00/12] tcg/riscv: Add support for vector LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-11 18:34 ` Richard Henderson
2024-09-18 5:14 ` LIU Zhiwei
2024-09-18 10:14 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 02/12] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-11 18:41 ` Richard Henderson
2024-09-18 5:17 ` LIU Zhiwei
2024-09-18 10:11 ` Richard Henderson
2024-09-18 10:43 ` LIU Zhiwei
2024-09-18 14:27 ` Richard Henderson
2024-09-20 4:01 ` 0x48 Swung
2024-09-20 4:27 ` LIU Zhiwei
2024-09-20 14:26 ` LIU Zhiwei
2024-09-21 15:56 ` 0x48 Swung
2024-09-21 17:17 ` Daniel Henrique Barboza
2024-09-20 11:26 ` Daniel Henrique Barboza
2024-09-20 11:37 ` Markus Armbruster [this message]
2024-09-11 13:26 ` [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops LIU Zhiwei
2024-09-11 22:57 ` Richard Henderson
2024-09-22 4:46 ` Richard Henderson
2024-09-23 4:46 ` LIU Zhiwei
2024-09-23 10:10 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 04/12] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-11 23:07 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 05/12] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 06/12] tcg/riscv: Implement vector cmp/cmpsel ops LIU Zhiwei
2024-09-11 23:14 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 07/12] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 08/12] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 09/12] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-11 13:26 ` [PATCH v4 10/12] tcg/riscv: Implement vector shi/s/v ops LIU Zhiwei
2024-09-11 23:15 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 11/12] tcg/riscv: Implement vector roti/v/x ops LIU Zhiwei
2024-09-11 23:24 ` Richard Henderson
2024-09-11 13:26 ` [PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
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