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Wed, 01 Dec 2021 16:23:26 +0000 Date: Wed, 01 Dec 2021 16:23:26 +0000 Message-ID: <87a6hkmgzl.wl-maz@kernel.org> From: Marc Zyngier To: Joey Gouly Cc: , , , , , , , , Subject: Re: [PATCH v1 2/3] arm64: add ID_AA64ISAR2_EL1 sys register In-Reply-To: <20211201120558.9140-3-joey.gouly@arm.com> References: <20211201120558.9140-1-joey.gouly@arm.com> <20211201120558.9140-3-joey.gouly@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org, nd@arm.com, alexandru.elisei@arm.com, catalin.marinas@arm.com, corbet@lwn.net, james.morse@arm.com, reijiw@google.com, suzuki.poulose@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211201_082332_033715_77B39678 X-CRM114-Status: GOOD ( 21.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 01 Dec 2021 12:05:57 +0000, Joey Gouly wrote: > > This is a new ID register, introduced in 8.7. > > Signed-off-by: Joey Gouly > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: James Morse > Cc: Alexandru Elisei > Cc: Suzuki K Poulose > Cc: Reiji Watanabe > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 10 ++++++++++ > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index 0f6d16faa540..a58e366f0b07 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -51,6 +51,7 @@ struct cpuinfo_arm64 { > u64 reg_id_aa64dfr1; > u64 reg_id_aa64isar0; > u64 reg_id_aa64isar1; > + u64 reg_id_aa64isar2; > u64 reg_id_aa64mmfr0; > u64 reg_id_aa64mmfr1; > u64 reg_id_aa64mmfr2; > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index adcab9009f9d..b4470b0eba69 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -182,6 +182,7 @@ > > #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) > #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) > +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) > > #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) > #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) > @@ -771,6 +772,15 @@ > #define ID_AA64ISAR1_GPI_NI 0x0 > #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 > > +/* id_aa64isar2 */ > +#define ID_AA64ISAR2_RPRES_SHIFT 4 > +#define ID_AA64ISAR2_WFXT_SHIFT 0 > + > +#define ID_AA64ISAR2_RPRES_8BIT 0x0 > +#define ID_AA64ISAR2_RPRES_12BIT 0x1 > +#define ID_AA64ISAR2_WFXT_NI 0x0 > +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x1 Could you also document the "fixed" version of WFxT (aka FEAT_WFxT2), where the register number is reported in ESR_EL2 when trapping? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel