From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 693EEC11D2F for ; Mon, 24 Feb 2020 14:24:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09D522080D for ; Mon, 24 Feb 2020 14:24:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09D522080D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 707E06E507; Mon, 24 Feb 2020 14:24:55 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 309896E507 for ; Mon, 24 Feb 2020 14:24:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2020 06:24:48 -0800 X-IronPort-AV: E=Sophos;i="5.70,480,1574150400"; d="scan'208";a="230664710" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.66.161]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2020 06:24:46 -0800 From: Jani Nikula To: Vandita Kulkarni , intel-gfx@lists.freedesktop.org In-Reply-To: <20200203124735.365-2-vandita.kulkarni@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20200203124735.365-1-vandita.kulkarni@intel.com> <20200203124735.365-2-vandita.kulkarni@intel.com> Date: Mon, 24 Feb 2020 16:24:43 +0200 Message-ID: <87a758t650.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [V7 1/9] drm/i915/dsi: Configure transcoder operation for command mode. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 03 Feb 2020, Vandita Kulkarni wrote: > Configure the transcoder to operate in TE GATE command mode > and take TE events from GPIO. > Also disable the periodic command mode, that GOP would have > programmed. > > v2: Disable util pin (Jani) > > Signed-off-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 52 ++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index d842e280699d..ce5e38c16201 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -744,6 +744,18 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, > tmp |= VIDEO_MODE_SYNC_PULSE; > break; > } > + } else { > + /* > + * FIXME: Retrieve this info from VBT. > + * As per the spec when dsi transcoder is operating > + * in TE GATE mode, TE comes from GPIO > + * which is UTIL PIN for DSI 0. > + * Also this GPIO would not be used for other > + * purposes is an assumption. > + */ > + tmp &= ~OP_MODE_MASK; > + tmp |= CMD_MODE_TE_GATE; > + tmp |= TE_SOURCE_GPIO; > } > > intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); > @@ -1016,6 +1028,32 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, > } > } > > +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, > + bool enable) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + u32 tmp; > + > + /* > + * used as TE i/p for DSI0, > + * for dual link/DSI1 TE is from slave DSI1 > + * through GPIO. > + */ > + if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) > + return; > + > + tmp = I915_READ(UTIL_PIN_CTL); > + > + if (enable) { > + tmp |= UTIL_PIN_DIRECTION_INPUT; > + tmp |= UTIL_PIN_ENABLE; > + } else { > + tmp &= ~UTIL_PIN_ENABLE; > + } > + I915_WRITE(UTIL_PIN_CTL, tmp); Please use intel_de_read() and intel_de_write(). > +} > + > static void > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > @@ -1037,6 +1075,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > /* setup D-PHY timings */ > gen11_dsi_setup_dphy_timings(encoder, crtc_state); > > + /* Since transcoder is configured to take events from GPIO */ > + gen11_dsi_config_util_pin(encoder, true); > + > /* step 4h: setup DSI protocol timeouts */ > gen11_dsi_setup_timeouts(encoder, crtc_state); > > @@ -1180,6 +1221,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) > enum transcoder dsi_trans; > u32 tmp; > > + /* disable periodic update mode */ > + if (is_cmd_mode(intel_dsi)) { > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp = I915_READ(DSI_CMD_FRMCTL(port)); > + tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE; > + I915_WRITE(DSI_CMD_FRMCTL(port), tmp); Ditto. With those fixed, Reviewed-by: Jani Nikula > + } > + } > + > /* put dsi link in ULPS */ > for_each_dsi_port(port, intel_dsi->ports) { > dsi_trans = dsi_port_to_transcoder(port); > @@ -1286,6 +1336,8 @@ static void gen11_dsi_disable(struct intel_encoder *encoder, > /* step3: disable port */ > gen11_dsi_disable_port(encoder); > > + gen11_dsi_config_util_pin(encoder, false); > + > /* step4: disable IO power */ > gen11_dsi_disable_io_power(encoder); > } -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx