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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Limit number of reads to stabilize rc6 counter reads
Date: Mon, 27 Mar 2017 14:30:38 +0300	[thread overview]
Message-ID: <87a887x8gx.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170327104509.GE10606@nuc-i3427.alporthouse.com>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> On Mon, Mar 27, 2017 at 01:07:58PM +0300, Mika Kuoppala wrote:
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > We have only 8bits of precise timestamps in which to complete our
>> > upper/load reads, along with the switch between precision. This is not
>> > always enough time to read the upper counter twice within the same time
>> > slice, leading to hard lockups. Limit the number of times to prevent
>> > an inifite loop (my fault for assuming we would have no trouble doing
>> > the write + reads fast enough).
>> >
>> 
>> We get here only with kasan enabled? Or even without?
>
> It quite possibly is just a kasan artefact. Though we are chasing severe
> latencies (>400us) due to mmio reads elsewhere (skl gt4e).

And with byt, even inside local_irq_disable/enable. I read that
there has been some pstate messups in the intel_idle. I just
hope that would be remedy, haven't tested yet.

-Mika


> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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  reply	other threads:[~2017-03-27 11:31 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-24 16:54 [PATCH] drm/i915: Limit number of reads to stabilize rc6 counter reads Chris Wilson
2017-03-24 17:14 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-03-27 10:07 ` [PATCH] " Mika Kuoppala
2017-03-27 10:45   ` Chris Wilson
2017-03-27 11:30     ` Mika Kuoppala [this message]
2017-03-27 12:23   ` Chris Wilson

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