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[73.207.178.95]) by smtp.gmail.com with ESMTPSA id d68sm2506402ywh.7.2017.01.19.16.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 19 Jan 2017 16:08:45 -0800 (PST) References: <20170119170507.16185-1-alex.bennee@linaro.org> <20170119170507.16185-27-alex.bennee@linaro.org> User-agent: mu4e 0.9.17; emacs 25.1.1 From: Pranith Kumar To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, pbonzini@redhat.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net, peter.maydell@linaro.org, claudio.fontana@huawei.com, bamvor.zhangjian@linaro.org, "open list\:ARM" Subject: Re: [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts In-reply-to: <20170119170507.16185-27-alex.bennee@linaro.org> Date: Thu, 19 Jan 2017 19:08:44 -0500 Message-ID: <87a8amr3sj.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-TUID: R2VzWvEeiHar Alex Bennée writes: > This enables the multi-threaded system emulation by default for ARMv7 > and ARMv8 guests using the x86_64 TCG backend. This is because on the > guest side: > > - The ARM translate.c/translate-64.c have been converted to > - use MTTCG safe atomic primitives > - emit the appropriate barrier ops > - The ARM machine has been updated to > - hold the BQL when modifying shared cross-vCPU state > - defer cpu_reset to async safe work > > All the host backends support the barrier and atomic primitives but > need to provide same-or-better support for normal load/store > operations. > > Signed-off-by: Alex Bennée > > +/* This defines the natural memory order supported by this > + * architecture before guarantees made by various barrier > + * instructions. > + * > + * The x86 has a pretty strong memory ordering which only really > + * allows for some stores to be re-ordered after loads. > + */ > +#include "tcg-mo.h" > + > +static inline int get_tcg_target_mo(void) > +{ > + return TCG_MO_ALL & ~TCG_MO_LD_ST; > +} > + Shouldn't this be TCG_MO_ALL & ~TCG_MO_ST_LD? Thanks, -- Pranith From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUMlB-0006IN-P8 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 19:08:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cUMlA-0004Rj-Tv for qemu-devel@nongnu.org; Thu, 19 Jan 2017 19:08:53 -0500 References: <20170119170507.16185-1-alex.bennee@linaro.org> <20170119170507.16185-27-alex.bennee@linaro.org> From: Pranith Kumar In-reply-to: <20170119170507.16185-27-alex.bennee@linaro.org> Date: Thu, 19 Jan 2017 19:08:44 -0500 Message-ID: <87a8amr3sj.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, pbonzini@redhat.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net, peter.maydell@linaro.org, claudio.fontana@huawei.com, bamvor.zhangjian@linaro.org, "open list:ARM" Alex Bennée writes: > This enables the multi-threaded system emulation by default for ARMv7 > and ARMv8 guests using the x86_64 TCG backend. This is because on the > guest side: > > - The ARM translate.c/translate-64.c have been converted to > - use MTTCG safe atomic primitives > - emit the appropriate barrier ops > - The ARM machine has been updated to > - hold the BQL when modifying shared cross-vCPU state > - defer cpu_reset to async safe work > > All the host backends support the barrier and atomic primitives but > need to provide same-or-better support for normal load/store > operations. > > Signed-off-by: Alex Bennée > > +/* This defines the natural memory order supported by this > + * architecture before guarantees made by various barrier > + * instructions. > + * > + * The x86 has a pretty strong memory ordering which only really > + * allows for some stores to be re-ordered after loads. > + */ > +#include "tcg-mo.h" > + > +static inline int get_tcg_target_mo(void) > +{ > + return TCG_MO_ALL & ~TCG_MO_LD_ST; > +} > + Shouldn't this be TCG_MO_ALL & ~TCG_MO_ST_LD? Thanks, -- Pranith