From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: Re: [PATCH] intel: Fix stencil buffer to be W tiled Date: Mon, 18 Jul 2011 08:57:10 -0700 Message-ID: <87aacbwpih.fsf@eliezer.anholt.net> References: <1310975703-20269-1-git-send-email-chad@chad-versace.us> <1310975703-20269-3-git-send-email-chad@chad-versace.us> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0469511068==" Return-path: In-Reply-To: <1310975703-20269-3-git-send-email-chad@chad-versace.us> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: mesa-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Chad Versace List-Id: intel-gfx@lists.freedesktop.org --===============0469511068== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wro= te: > diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dr= i/intel/intel_fbo.c > index 1669af2..507cc33 100644 > --- a/src/mesa/drivers/dri/intel/intel_fbo.c > +++ b/src/mesa/drivers/dri/intel/intel_fbo.c > @@ -173,6 +173,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * = ctx, struct gl_renderbuffer >=20=20 > if (irb->Base.Format =3D=3D MESA_FORMAT_S8) { > /* > + * The stencil buffer is W tiled. However, we request from the ker= nel a > + * non-tiled buffer because the GTT is incapable of W fencing. > + * > * The stencil buffer has quirky pitch requirements. From Vol 2a, > * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch": > * The pitch must be set to 2x the value computed based on widt= h, as > @@ -180,14 +183,14 @@ intel_alloc_renderbuffer_storage(struct gl_context = * ctx, struct gl_renderbuffer > * To accomplish this, we resort to the nasty hack of doubling the= drm > * region's cpp and halving its height. > * > - * If we neglect to double the pitch, then drm_intel_gem_bo_map_gt= t() > - * maps the memory incorrectly. > + * If we neglect to double the pitch, then render corruption occur= s. > */ > irb->region =3D intel_region_alloc(intel->intelScreen, > - I915_TILING_Y, > + I915_TILING_NONE, > cpp * 2, > - width, > - height / 2, > + ALIGN(width, 64), > + /* XXX: Maybe align to 128? */ > + ALIGN(height / 2, 64), > GL_TRUE); > if (!irb->region) > return false; This looks like it would fail on a buffer with height =3D 129. Doesn't seem like 128 pitch requirement would be needed -- has it been tested? > diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/d= ri/intel/intel_span.c > index 153803f..d306432 100644 > --- a/src/mesa/drivers/dri/intel/intel_span.c > +++ b/src/mesa/drivers/dri/intel/intel_span.c > @@ -131,38 +131,77 @@ intel_set_span_functions(struct intel_context *inte= l, > int miny =3D 0; \ > int maxx =3D rb->Width; \ > int maxy =3D rb->Height; \ > - int stride =3D rb->RowStride; \ > - uint8_t *buf =3D rb->Data; \ > + \ > + /* \ > + * Here we ignore rb->Data and rb->RowStride as set by \ > + * intelSpanRenderStart. Since intel_offset_S8 decodes the W tile \ > + * manually, the region's *real* base address and stride is \ > + * required. \ > + */ \ > + struct intel_renderbuffer *irb =3D intel_renderbuffer(rb); \ > + uint8_t *buf =3D irb->region->buffer->virtual; \ > + unsigned stride =3D irb->region->pitch; \ > + unsigned height =3D 2 * irb->region->height; \ > + bool flip =3D rb->Name =3D=3D 0; \ >=20=20 > -/* Don't flip y. */ > #undef Y_FLIP > -#define Y_FLIP(y) y > +#define Y_FLIP(y) ((1 - flip) * y + flip * (height - 1 - y)) The flip is usually handled by a scale and bias variable, so that Y_FLIP is ((y) * scale + bias). I think it'll produce less code, since Y_FLIP is used a lot. --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEARECAAYFAk4kV9YACgkQHUdvYGzw6vdp/wCfSFQPddmlEzXWPN+wBla1UXDk AOsAoIZ0CH6qVjpp3jFyFWKlWc8niaop =RzA7 -----END PGP SIGNATURE----- --=-=-=-- --===============0469511068== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0469511068==--