From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Aug 2004 06:30:47 +0100 (BST) Received: from mx1.redhat.com ([IPv6:::ffff:66.187.233.31]:40633 "EHLO mx1.redhat.com") by linux-mips.org with ESMTP id ; Tue, 3 Aug 2004 06:30:42 +0100 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i735Uee1015116; Tue, 3 Aug 2004 01:30:40 -0400 Received: from localhost (mail@vpnuser3.surrey.redhat.com [172.16.9.3]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i735Uda22551; Tue, 3 Aug 2004 01:30:39 -0400 Received: from rsandifo by localhost with local (Exim 3.35 #1) id 1Brrsk-0000D2-00; Tue, 03 Aug 2004 06:30:38 +0100 To: Nigel Stephens Cc: "Maciej W. Rozycki" , Ralf Baechle , Richard Henderson , gcc-patches@gcc.gnu.org, linux-mips@linux-mips.org Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bit targets References: <87hds49bmo.fsf@redhat.com> <20040719213801.GD14931@redhat.com> <20040723202703.GB30931@redhat.com> <20040723211232.GB5138@linux-mips.org> <410E9E25.7080104@mips.com> From: Richard Sandiford Date: Tue, 03 Aug 2004 06:30:38 +0100 In-Reply-To: <410E9E25.7080104@mips.com> (Nigel Stephens's message of "Mon, 02 Aug 2004 21:03:49 +0100") Message-ID: <87acxcbxfl.fsf@redhat.com> User-Agent: Gnus/5.1006 (Gnus v5.10.6) Emacs/21.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 5581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rsandifo@redhat.com Precedence: bulk X-list: linux-mips Nigel Stephens writes: > I have a patch against gcc-3.4 which makes the 64-bit inline shifts > somewhat smaller on ISAs which include the conditional move > (movz/movn) instructions, but more importantly removes all branches > from the inline code - which can be very expensive on long pipeline > CPUs, since in this sort of code they tend to cause many branch > mispredicts. Let me know if you want me to extract the patch - here's > a table of the number of instructions generated by the original md > pattern and the patched version: > > Instructions > Old New > ashldi3 12 9 > ashrdi3 12 12 > lshrdi3 12 9 > > > If people really don't like the inline expansion, then maybe it could be > enabled or disabled by a new -m option. IMO, controlling with optimize_size would be enough. But it sounds from your description like the patch just adds a new hard-coded multi-insn asm string. Is that right? If so, I'd really like to avoid that. It would much better IMO if we handle this in the target-independent parts of the compiler. We can already open-code certain non-native operations, it's "just" that wide shifts are a missing case. If we handle it in a target-independent way, with each insn exposed separately, we will be able to optimize special cases better. We'll also get the usual scheduling benefits. Richard