From: Thomas Gleixner <tglx@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>,
"biju.das.au" <biju.das.au@gmail.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"biju.das.au" <biju.das.au@gmail.com>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support
Date: Wed, 01 Apr 2026 13:22:26 +0200 [thread overview]
Message-ID: <87bjg37wnh.ffs@tglx> (raw)
In-Reply-To: <TYCPR01MB11332DCA62A7B45AF2583DC238650A@TYCPR01MB11332.jpnprd01.prod.outlook.com>
On Wed, Apr 01 2026 at 07:30, Biju Das wrote:
>> From: Thomas Gleixner <tglx@kernel.org>
>>
>> How is that not RMW?
>
> It is not a shared reg, as there is only a single NMI interrupt and hwirq is always 0.
> I will drop BIT(hwirq) to avoid confusion related to the shared register.
>
>>
>> I assume that you want to explain that it's not a RMW on a shared register, right?
>
> Bit16 - NSMON: NMI pin signal level monitor register (read only)
> Bit0 - NSTAT: NMI interrupt status. Writing is allowed only when NSTAT is 1.
>
> Yes, I will add a comment: Writing is allowed only when NSTAT is 1.
Yes please.
prev parent reply other threads:[~2026-04-01 11:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-28 10:33 [PATCH 0/3] irqchip/renesas-rzg2l: Bug fixes and NMI support Biju
2026-03-28 10:33 ` [PATCH 1/3] irqchip/renesas-rzg2l: Fix shared IRQ bit not cleared on free Biju
2026-03-28 10:33 ` [PATCH 2/3] irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in rzg2l_irq_set_type() Biju
2026-03-28 10:33 ` [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support Biju
2026-03-28 16:19 ` Wolfram Sang
2026-03-31 17:35 ` Biju Das
2026-03-31 16:15 ` Thomas Gleixner
2026-03-31 17:10 ` Biju Das
2026-03-31 20:29 ` Thomas Gleixner
2026-04-01 7:30 ` Biju Das
2026-04-01 11:22 ` Thomas Gleixner [this message]
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