Re: [PATCH RFC 1/3] arm: handle demuxed ID registers

[Cornelia Huck <cohuck@redhat.com>]

On Wed, Jan 21 2026, Jonathan Cameron <jonathan.cameron@huawei.com> wrote:

> On Mon, 19 Jan 2026 18:27:30 +0100
> Cornelia Huck <cohuck@redhat.com> wrote:
>> @@ -1083,6 +1102,7 @@ struct ArchCPU {
>>          uint32_t dbgdevid1;
>>          uint64_t reset_pmcr_el0;
>>          uint64_t idregs[NUM_ID_IDX];
>> +        uint64_t idregs_demux[NUM_ID_DEMUX_IDX][16];
> Hi,
>
> Trivial, but I'd like a comment on why 16. I assume because that's
> the biggest you've seen so far (8 levels, 2 types for CCSIDR)
> Just good to have a bread crumb here for future readers.

Yes, this came in via the current ccsidr[] sizing (which also might not
be quite the right thing to use, given that we could have 2*7 + 7
entries with FEAT_MTE2); I'm not at all sure whether that's a reasonable
value, but I'll certainly add a comment if we agree that it is. Or maybe
make it a #define.

>
> Otherwise seems reasonable to me.

Thanks for looking!

>>      } isar;
>>      uint64_t midr;
>>      uint32_t revidr;