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Tue, 07 Oct 2025 14:17:22 -0700 (PDT) Received: from osv.localdomain ([89.175.180.246]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-375f3b64349sm13648291fa.33.2025.10.07.14.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 14:17:21 -0700 (PDT) From: Sergey Organov To: Fabio Estevam Cc: linux-kernel@vger.kernel.org, Ulf Hansson , Shawn Guo , "Rob Herring (Arm)" Subject: Re: ARM iMX6sx board fails to boot with kernel 6.17 References: <87v7l03pqe.fsf@osv.gnss.ru> <87o6qjaiz7.fsf@osv.gnss.ru> <87jz17afpb.fsf@osv.gnss.ru> Date: Wed, 08 Oct 2025 00:17:20 +0300 In-Reply-To: (Fabio Estevam's message of "Mon, 6 Oct 2025 23:05:06 -0300") Message-ID: <87bjmih0nz.fsf@osv.gnss.ru> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Hi Fabio, Fabio Estevam writes: > On Mon, Oct 6, 2025 at 6:22 PM Sergey Organov wrote: > >> It is built form multiple .dtsi, so I figure I attach the one after >> pre-processing stage. Please let me know if you'd prefer I rather >> manually insert all the custom .dtsi into a single .dts, and send that >> one instead. > > This format is hard to follow. > > To make things easier for debugging, you could create a minimal board > dts file with only UART and eMMC nodes to reproduce the problem. Please see attached minimum DTS. Maybe it misses something? Shouldn't DTS describe how eMMC chip is powered, provided it's powered from NXP MMPF0100F6ANES PMIC? I didn't find any hints in other DTS'es. > It's not clear to me the relationship between the ANATOP regulators > and the eMMC power on your board. Sheer mystery for me. The point of hang is not entirely deterministic either, that suggests it's some power problem indeed. It may hang after random line among the following depending on exact build and sometimes even from run-to-run: ... mmc0: SDHCI controller on 219c000.mmc [219c000.mmc] using ADMA Loading compiled-in X.509 certificates clk: Disabling unused clocks PM: genpd: Disabling unused power domains check access for rdinit=/init failed: -2, ignoring Waiting for root device /dev/mmcblk0p2... Also, I just tried to compile entire kernel with -DDEBUG, and it starts to see the eMMC, though still hangs not ever mounting the root FS: mmc0: SDHCI controller on 219c000.mmc [219c000.mmc] using ADMA Loading compiled-in X.509 certificates mmc0: new high speed DDR MMC card at address 0001 mmcblk0: mmc0:0001 IX2964 58.3 GiB mmcblk0: p1 p2 p3 p4 < p5 p6 > mmcblk0boot0: mmc0:0001 IX2964 4.00 MiB mmcblk0boot1: mmc0:0001 IX2964 4.00 MiB mmcblk0rpmb: mmc0:0001 IX2964 4.00 MiB, chardev (246:0) clk: Disabling unused clocks PM: genpd: Disabling unused power domains check access for rdinit=/init failed: -2, ignoring -- Sergey Organov --=-=-= Content-Type: text/plain Content-Disposition: attachment; filename=javad-minimum.dts Content-Description: troublesome minimum dts /dts-v1/; #include "../imx6sx.dtsi" / { compatible = "javad,imx6sx", "fsl,imx6sx"; chosen { stdout-path = &uart1; }; aliases { mmc0 = &usdhc4; mmc1 = &usdhc3; mmc2 = &usdhc2; mmc3 = &usdhc1; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; &usdhc4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; non-removable; keep-power-in-suspend; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; dma-names = ""; uart-has-rtscts; status = "okay"; }; &iomuxc { pinctrl-names = "default"; imx6x-sdb { pinctrl_usdhc4: usdhc4grp { fsl,pins = < MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x1b0b1 MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x1b0b1 >; }; }; }; --=-=-=--