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From: Thomas Gleixner <tglx@linutronix.de>
To: Prabhakar <prabhakar.csengg@gmail.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
Date: Mon, 03 Jun 2024 14:40:06 +0200	[thread overview]
Message-ID: <87bk4i6vyx.ffs@tglx> (raw)
In-Reply-To: <20240430141438.132838-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

On Tue, Apr 30 2024 at 15:14, Prabhakar wrote:
> +
> +static void rzfive_irqc_irq_disable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, false);
> +	irq_chip_disable_parent(d);
> +}
> +
> +static void rzfive_irqc_irq_enable(struct irq_data *d)
> +{
> +	rzfive_tint_irq_endisable(d, true);
> +	irq_chip_enable_parent(d);
> +}

This looks wrong. Enable/disable should be symmetric vs. ordering, no?

Thanks,

        tglx

  reply	other threads:[~2024-06-03 12:40 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-30 14:14 [PATCH v4 0/2] Add IAX45 support for RZ/Five SoC Prabhakar
2024-04-30 14:14 ` [PATCH v4 1/2] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document " Prabhakar
2024-04-30 14:14 ` [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for " Prabhakar
2024-06-03 12:40   ` Thomas Gleixner [this message]
2024-06-04 17:29     ` Lad, Prabhakar

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