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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Tejas Upadhyay <tejas.upadhyay@intel.com>,
	intel-xe@lists.freedesktop.org
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: Re: [PATCH] drm/xe/xe2lpm: Add Wa_15015404425
Date: Wed, 29 May 2024 10:36:23 +0300	[thread overview]
Message-ID: <87bk4pkr2g.fsf@intel.com> (raw)
In-Reply-To: <20240524063228.127423-1-tejas.upadhyay@intel.com>

On Fri, 24 May 2024, Tejas Upadhyay <tejas.upadhyay@intel.com> wrote:
> Wa_15015404425 applies to xe2_lpm all steppings
>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h |  1 +
>  drivers/gpu/drm/xe/xe_mmio.c      | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 722fb6dbb72e..07c8a23bd7c2 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -42,6 +42,7 @@
>  #define STOLEN_RESERVED				XE_REG(0x1082c0)
>  #define   WOPCM_SIZE_MASK			REG_GENMASK64(9, 7)
>  
> +#define MEDIA_DUMMY_REG				XE_REG(0x138000)
>  #define MTL_RP_STATE_CAP			XE_REG(0x138000)
>  
>  #define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index ff7a7cf99530..e1dc87078387 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -450,6 +450,21 @@ int xe_mmio_init(struct xe_device *xe)
>  	return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
>  }
>  
> +static void mmio_flush_pending_writes(struct xe_gt *gt)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +
> +	if (!(xe->info.platform == XE_LUNARLAKE))
> +		return;
> +
> +	if (xe_gt_is_media_type(gt) &&  MEDIA_VER(xe) == 20) {
> +		int itr = 4;
> +		/* 4 dummy writes */
> +		while (itr--)

If you need to do something N times, the paradigm loop is:

	for (i = 0; i < N; i++)

and nobody has to pause to consider the loop condition.

BR,
Jani.

> +			xe_mmio_write32(gt, MEDIA_DUMMY_REG, 0);
> +	}
> +}
> +
>  u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
> @@ -479,6 +494,9 @@ u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
>  	struct xe_tile *tile = gt_to_tile(gt);
>  	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
>  
> +	/* Wa_15015404425 */
> +	mmio_flush_pending_writes(gt);
> +
>  	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
>  }

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2024-05-29  7:36 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-24  6:32 [PATCH] drm/xe/xe2lpm: Add Wa_15015404425 Tejas Upadhyay
2024-05-24  6:37 ` ✓ CI.Patch_applied: success for " Patchwork
2024-05-24  6:37 ` ✓ CI.checkpatch: " Patchwork
2024-05-24  6:38 ` ✓ CI.KUnit: " Patchwork
2024-05-24  6:50 ` ✓ CI.Build: " Patchwork
2024-05-24  6:52 ` ✓ CI.Hooks: " Patchwork
2024-05-24  6:54 ` ✓ CI.checksparse: " Patchwork
2024-05-24  7:25 ` ✓ CI.BAT: " Patchwork
2024-05-24  8:20 ` ✗ CI.FULL: failure " Patchwork
2024-05-28 17:05 ` [PATCH] " Cavitt, Jonathan
2024-05-28 23:03 ` Matt Roper
2024-05-29  6:39   ` Upadhyay, Tejas
2024-05-29 20:03     ` Matt Roper
2024-07-02  5:34       ` Upadhyay, Tejas
2024-05-29 10:56   ` Upadhyay, Tejas
2024-05-29  7:36 ` Jani Nikula [this message]
2024-05-29 12:39   ` Upadhyay, Tejas
2024-05-29 12:45     ` Jani Nikula

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