From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/bios: Fixup h/vsync_end instead of h/vtotal
Date: Thu, 21 Sep 2023 10:17:32 +0300 [thread overview]
Message-ID: <87bkdwq9kj.fsf@intel.com> (raw)
In-Reply-To: <20230920211934.14920-2-ville.syrjala@linux.intel.com>
On Thu, 21 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have the same h/vsync_end vs. h/vtotal quirk in the VBT parser
> that was also present in EDID parser. Adjust the VBT parser the
> same way as was done for hte EDID parser to fixup h/vsync_end
> instead of h/vtotal. While I'm not currently aware of any machines
> that need this for the VBT it seems prudent to keep both parsers
> in sync.
>
> And while at it let's add some debugs here as well. A bit
> lackluster but didn't feel like plumbing the connector all
> the way down at this time.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 23 +++++++++++++++--------
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index f735b035436c..863ff54fffd1 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -521,7 +521,8 @@ static void init_bdb_blocks(struct drm_i915_private *i915,
> }
>
> static void
> -fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
> +fill_detail_timing_data(struct drm_i915_private *i915,
> + struct drm_display_mode *panel_fixed_mode,
> const struct lvds_dvo_timing *dvo_timing)
> {
> panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
> @@ -561,11 +562,17 @@ fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
> panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
> dvo_timing->vimage_lo;
>
> - /* Some VBTs have bogus h/vtotal values */
> - if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
> - panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
> - if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
> - panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
> + /* Some VBTs have bogus h/vsync_end values */
> + if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) {
> + drm_dbg_kms(&i915->drm, "reducing hsync_end %d->%d\n",
> + panel_fixed_mode->hsync_end, panel_fixed_mode->htotal);
> + panel_fixed_mode->hsync_end = panel_fixed_mode->htotal;
> + }
> + if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) {
> + drm_dbg_kms(&i915->drm, "reducing vsync_end %d->%d\n",
> + panel_fixed_mode->vsync_end, panel_fixed_mode->vtotal);
> + panel_fixed_mode->vsync_end = panel_fixed_mode->vtotal;
> + }
>
> drm_mode_set_name(panel_fixed_mode);
> }
> @@ -849,7 +856,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
> if (!panel_fixed_mode)
> return;
>
> - fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
> + fill_detail_timing_data(i915, panel_fixed_mode, panel_dvo_timing);
>
> panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
>
> @@ -1134,7 +1141,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915,
> if (!panel_fixed_mode)
> return;
>
> - fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
> + fill_detail_timing_data(i915, panel_fixed_mode, &dtds->dtds[index]);
>
> panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
--
Jani Nikula, Intel
next prev parent reply other threads:[~2023-09-21 7:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-20 21:19 [Intel-gfx] [PATCH v2 1/2] drm/edid: Fixup h/vsync_end instead of h/vtotal Ville Syrjala
2023-09-20 21:19 ` Ville Syrjala
2023-09-20 21:19 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/bios: " Ville Syrjala
2023-09-20 21:19 ` Ville Syrjala
2023-09-21 7:17 ` Jani Nikula [this message]
2023-09-21 2:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/edid: " Patchwork
2023-09-21 2:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-21 3:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-09-21 7:15 ` [Intel-gfx] [PATCH v2 1/2] " Jani Nikula
2023-09-21 7:15 ` Jani Nikula
2023-09-21 10:44 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] " Patchwork
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