From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E8C03F817 for ; Tue, 19 Sep 2023 16:31:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7114C433C9; Tue, 19 Sep 2023 16:31:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695141067; bh=5a+elSpKhcGOSKULvNRpmeAVuPK0jEBaAiyUS/Utgg0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XSUaJcOxScCOSgohi0fqmrftMabZq/HFkz+n4molps3vikQJsgrw7cW9grFP9lhrb 4i0C1tlI8z4EBERM4kQHjZO88Q8nclyKZBNOZIw+vmji6EogCZryDQxntBBzLORgwS Xed3ufZOP4d9qCi5R9s5twMAkSwoKWLElMOKEzmDOV2b1mbC0RVvGd6SjKh7amGIVc BXCM505VxcKtVPt+9/vVdCCj3IHI/3iReL9EMe/opdXJaEcSdoTsacjZ9MJHd/qCTc GWcO2qTIhLkGyYFOoOIkN2N6/3lQkkurLrxOZszOFhIVRNRZbu5hdYw39t6D59537E Ay/xgyYSYA5Kw== Received: from [104.132.45.96] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qidcv-00EOIj-DZ; Tue, 19 Sep 2023 17:31:05 +0100 Date: Tue, 19 Sep 2023 17:31:04 +0100 Message-ID: <87bkdy3z1z.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kvmarm@lists.linux.dev" Subject: Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization In-Reply-To: <00087AB1-3F94-4D3B-8498-3CE3AEDFE6FA@oracle.com> References: <20230913185209.32282-1-miguel.luis@oracle.com> <20230913185209.32282-3-miguel.luis@oracle.com> <868r93es5a.wl-maz@kernel.org> <00087AB1-3F94-4D3B-8498-3CE3AEDFE6FA@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 104.132.45.96 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 19 Sep 2023 15:54:53 +0100, Miguel Luis wrote: >=20 > Hi Marc, >=20 > > On 18 Sep 2023, at 09:40, Marc Zyngier wrote: > >=20 > > Hi Miguel, > >=20 > > On Wed, 13 Sep 2023 19:52:07 +0100, > > Miguel Luis wrote: > >>=20 > >> Some _EL1 registers got included in the _EL2 ranges, which are not > >> affected by NV. Remove them and fine grain the ranges to exclusively > >> include the _EL2 ones. > >>=20 > >> Signed-off-by: Miguel Luis > >> --- > >> arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++----- > >> 1 file changed, 38 insertions(+), 6 deletions(-) > >>=20 > >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-= nested.c > >> index 9ced1bf0c2b7..9aa1c06abdb7 100644 > >> --- a/arch/arm64/kvm/emulate-nested.c > >> +++ b/arch/arm64/kvm/emulate-nested.c > >> @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config enco= ding_to_cgt[] __initconst =3D { > >> SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), > >> /* All _EL2 registers */ > >> SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), > >> - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), > >> + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV), > >=20 > > It would be good if the commit message explained that you are folding > > SPSR/ELR into the existing range. Also, please keep the two ends of > > the ranges vertically aligned. > >=20 >=20 > OK. >=20 > >> /* Skip the SP_EL1 encoding... */ > >> - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), > >> - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), > >> - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), > >> - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), > >> + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), > >> + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV), > >> + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, > >> + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, > >> + * VMECID_P_EL2. > >> + */ > >=20 > > Please follow the kernel comment format. Also, why are you skipping > > the MEC registers, but not the MPAM ones? At least indicate a > > rationale for this. > >=20 >=20 > I=E2=80=99m not aware of any exceptions for MPAM registers, although there > are for MEC when HCR_EL2.NV2 is 0. Then this rationale should probably be captured here. >=20 > >> SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), > >> - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), > >> + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV), > >> + /* ICH_AP0R_EL2 */ > >> + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, > >> + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), > >> + /* ICH_AP1R_EL2 */ > >> + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, > >> + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), > >> + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5), > >> + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV), > >> + /* ICH_LR_EL2 */ > >> + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV), > >> + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV), > >=20 > > You could describe all the LRs a single range. > >=20 >=20 > Should we skip the gap between LR7 - LR8 ? Which gap? LRn n described by (3,4,12,12,n) when n is in [0-7], and (3,4,12,13,n-8) when n is in [8-15]. These two ranges are contiguous. >=20 > >> + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1), > >> + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV), > >> + /* skip AMEVCNTVOFF0_EL2 and AMEVCNTVOFF1_EL2 */ > >=20 > > Why? >=20 > I didn=E2=80=99t find its definition TBH although these could use a singl= e range. D19.6.11 and following? Thanks, M. --=20 Without deviation from the norm, progress is not possible. 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