All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add helper function for getting number of VDSC engines
Date: Tue, 04 Jul 2023 15:17:10 +0300	[thread overview]
Message-ID: <87bkgr27nd.fsf@intel.com> (raw)
In-Reply-To: <20230704103107.11237-2-stanislav.lisovskiy@intel.com>

On Tue, 04 Jul 2023, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> Currently we are using dsc_split and bigjoiner variables for determining
> amount of VDSC instances, however that might change in future, if we happen
> to have more of those.
> So lets pack all that logic into single function for convenience, so that
> at least this isn't hardcoded throughout the whole VDSC code.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++++++++----
>  drivers/gpu/drm/i915/display/intel_vdsc.h |  1 +
>  2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index bd9116d2cd76..2811810a5eb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -293,6 +293,16 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>  		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>  }
>  
> +u8 intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)

s/u8/int/

> +{
> +	u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
> +
> +	if (crtc_state->bigjoiner_pipes)
> +		num_vdsc_instances *= 2;
> +
> +	return num_vdsc_instances;
> +}
> +
>  static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -303,11 +313,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  	u32 pps_val = 0;
>  	u32 rc_buf_thresh_dword[4];
>  	u32 rc_range_params_dword[8];
> -	u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
>  	int i = 0;
> -
> -	if (crtc_state->bigjoiner_pipes)
> -		num_vdsc_instances *= 2;
> +	u8 num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>  
>  	/* Populate PICTURE_PARAMETER_SET_0 registers */
>  	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 8763f00fa7e2..94a7652498e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -22,6 +22,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
>  struct intel_crtc *intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc);
> +u8 intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
>  void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>  			     const struct intel_crtc_state *crtc_state);
>  void intel_dsc_dp_pps_write(struct intel_encoder *encoder,

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2023-07-04 12:17 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-04 10:31 [Intel-gfx] [PATCH 0/2] Calculate CDCLK more properly when DSC is enabled Stanislav Lisovskiy
2023-07-04 10:31 ` [Intel-gfx] [PATCH 1/2] drm/i915: Add helper function for getting number of VDSC engines Stanislav Lisovskiy
2023-07-04 12:17   ` Jani Nikula [this message]
2023-07-04 10:31 ` [Intel-gfx] [PATCH 2/2] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate Stanislav Lisovskiy
2023-07-04 11:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Calculate CDCLK more properly when DSC is enabled Patchwork
2023-07-04 11:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-04 12:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-04 16:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2023-07-04 13:17 [Intel-gfx] [PATCH 0/2] " Stanislav Lisovskiy
2023-07-04 13:17 ` [Intel-gfx] [PATCH 1/2] drm/i915: Add helper function for getting number of VDSC engines Stanislav Lisovskiy
2023-07-10  6:10   ` Nautiyal, Ankit K

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87bkgr27nd.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=stanislav.lisovskiy@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.