All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
Date: Wed, 17 May 2023 18:49:51 -0700	[thread overview]
Message-ID: <87bkii4dds.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20230517205542.3680895-7-umesh.nerlige.ramappa@intel.com>

On Wed, 17 May 2023 13:55:41 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Reserve some bits in the counter config namespace which will carry the
> tile id and prepare the code to handle this.
>
> No per tile counters have been added yet.
>
> v2:
> - Fix checkpatch issues
> - Use 4 bits for gt id in non-engine counters. Drop FIXME.
> - Set MAX GTs to 4. Drop FIXME.
>
> v3: (Ashutosh, Tvrtko)
> - Drop BUG_ON that would never fire
> - Make enable u64
> - Pull in some code from next patch
>
> v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
>
> v5: s/u64/u32 where needed (Ashutosh)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

  reply	other threads:[~2023-05-18  1:50 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-17 20:55 [Intel-gfx] [PATCH v6 0/7] Add MTL PMU support for multi-gt Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 1/7] drm/i915/pmu: Change bitmask of enabled events to u32 Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 2/7] drm/i915/pmu: Support PMU for all engines Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 3/7] drm/i915/pmu: Skip sampling engines with no enabled counters Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 4/7] drm/i915/pmu: Transform PMU parking code to be GT based Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 5/7] drm/i915/pmu: Add reference counting to the sampling timer Umesh Nerlige Ramappa
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters Umesh Nerlige Ramappa
2023-05-18  1:49   ` Dixit, Ashutosh [this message]
2023-05-17 20:55 ` [Intel-gfx] [PATCH v6 7/7] drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa
2023-05-17 21:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt Patchwork
2023-05-17 21:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87bkii4dds.wl-ashutosh.dixit@intel.com \
    --to=ashutosh.dixit@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=umesh.nerlige.ramappa@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.