All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: DG2 intermediate DP source rates are different from CNL+
Date: Tue, 17 Aug 2021 08:40:58 +0300	[thread overview]
Message-ID: <87bl5wiq6t.fsf@intel.com> (raw)
In-Reply-To: <20210816204927.GK1556418@mdroper-desk1.amr.corp.intel.com>

On Mon, 16 Aug 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Aug 13, 2021 at 03:33:30PM +0300, Jani Nikula wrote:
>> DG2 has 243000 but not 648000.
>
> Am I looking in the wrong place?  When I check the bspec page I still
> see:
>
>         eDP/DP link bit rates: 1.62, 2.16, 2.7, 3.24, 4.32, 5.4, 6.48,
>         8.1 GHz, SSC and Non-SSC
>
> which matches the ICL rates list (i.e., 648000 included, but no
> reference to 243000).

I see the same thing. I can see no recent edits on the page either, so I
can only assume I've screwed up something, somehow when I wrote the
patch.

Never mind, and sorry for the noise.

BR,
Jani.



>
>
> Matt
>
>> 
>> Bspec: 54034
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 75d4ebc66941..e21de08fea32 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -247,6 +247,9 @@ static void
>>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  {
>>  	/* The values must be in increasing order */
>> +	static const int dg2_rates[] = {
>> +		162000, 216000, 243000, 270000, 324000, 432000, 540000, 810000,
>> +	};
>>  	static const int icl_rates[] = {
>>  		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
>>  	};
>> @@ -272,7 +275,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  	drm_WARN_ON(&dev_priv->drm,
>>  		    intel_dp->source_rates || intel_dp->num_source_rates);
>>  
>> -	if (DISPLAY_VER(dev_priv) >= 11) {
>> +	if (IS_DG2(dev_priv)) {
>> +		source_rates = dg2_rates;
>> +		size = ARRAY_SIZE(dg2_rates);
>> +	} else if (DISPLAY_VER(dev_priv) >= 11) {
>>  		source_rates = icl_rates;
>>  		size = ARRAY_SIZE(icl_rates);
>>  		if (IS_JSL_EHL(dev_priv))
>> -- 
>> 2.20.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

      reply	other threads:[~2021-08-17  5:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-13 12:33 [Intel-gfx] [PATCH] drm/i915/dg2: DG2 intermediate DP source rates are different from CNL+ Jani Nikula
2021-08-13 15:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-08-13 18:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-16 20:49 ` [Intel-gfx] [PATCH] " Matt Roper
2021-08-17  5:40   ` Jani Nikula [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87bl5wiq6t.fsf@intel.com \
    --to=jani.nikula@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.